PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION
    2.
    发明申请
    PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION 审中-公开
    针对10G以太网物理层解决方案优化的PLD架构

    公开(公告)号:WO2009126267A3

    公开(公告)日:2010-01-14

    申请号:PCT/US2009002188

    申请日:2009-04-07

    CPC classification number: H04L49/30 H04L49/352

    Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

    Abstract translation: 集成电路(例如可编程集成电路,例如可编程微控制器,可编程逻辑器件等)包括可编程电路和10吉比特以太网(10GbE)收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理(PHY)层。 该集成电路然后可以耦合到光收发器模块,以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

    METHOD TO DIGITIZE ANALOG SIGNALS IN A SYSTEM UTILIZING DYNAMIC ANALOG TEST MULTIPLEXER FOR DIAGNOSTICS
    3.
    发明申请
    METHOD TO DIGITIZE ANALOG SIGNALS IN A SYSTEM UTILIZING DYNAMIC ANALOG TEST MULTIPLEXER FOR DIAGNOSTICS 审中-公开
    数字化模拟信号的方法利用动态模拟测试多路复用器进行诊断

    公开(公告)号:WO2010051244A2

    公开(公告)日:2010-05-06

    申请号:PCT/US2009062028

    申请日:2009-10-26

    CPC classification number: G01R31/3167

    Abstract: An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

    Abstract translation: 介绍了一种能够监测模拟模块内部模拟电压的集成电路。 该集成电路有一个模拟测试多路复用器(mux),其输入端连接到模拟模块内部感兴趣的模拟电压。 模拟测试多路复用器将选定的模拟电压从模拟模块引导至模拟测试多路复用器的输出。 该集成电路还包括模拟监视状态机,其向模拟测试多路复用器提供选择位,使得能够随机访问模拟块内的模拟电压。 集成电路还包括模数转换器,用于将来自模拟测试多路复用器的选定模拟电压转换为数字表示。

    High-speed serial data signal transmitter driver circuitry
    4.
    发明专利
    High-speed serial data signal transmitter driver circuitry 审中-公开
    高速串行数据信号发射机驱动电路

    公开(公告)号:JP2009147948A

    公开(公告)日:2009-07-02

    申请号:JP2008320310

    申请日:2008-12-16

    CPC classification number: H04L25/028

    Abstract: PROBLEM TO BE SOLVED: To provide high-speed serial digital data signal transmitter driver circuitry.
    SOLUTION: The present invention relates to transmitter driver circuitry for outputting a high-speed serial data signal having a serial bit rate in the range of about 10 Gbps, including H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor forming a portion of the H-tree driver circuitry further provides electrostatic discharge protection for the circuitry.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题:提供高速串行数字数据信号发射器驱动电路。 解决方案:本发明涉及用于输出具有约10Gbps范围内的串行比特率的高速串行数据信号的发射机驱动器电路,包括仅具有主驱动级和后级的H树驱动器电路 tap驱动阶段。 形成H树驱动器电路的一部分的至少一个晶体管进一步为电路提供静电放电保护。 版权所有(C)2009,JPO&INPIT

    Protocol-agnostic automatic rate negotiation for high-speed serial interface in programmable logic device
    5.
    发明专利
    Protocol-agnostic automatic rate negotiation for high-speed serial interface in programmable logic device 审中-公开
    可编程逻辑器件中高速串行接口的协议自动比率自动调节

    公开(公告)号:JP2008236738A

    公开(公告)日:2008-10-02

    申请号:JP2008037812

    申请日:2008-02-19

    CPC classification number: G06F13/385 H03K19/177 H03K19/17744 H04L5/1446

    Abstract: PROBLEM TO BE SOLVED: To provide a rate negotiation independent of a protocol in use in a PLD receiver-transmitter.
    SOLUTION: A method for determining a data rate in a serial interface channel for a programmable logic device operating at a clock rate includes; monitoring the channel for occurrence of a single bit transition, and concluding that the data rate is virtually a multiple of the clock rate based on detection of a plurality of single bit transitions in a predefined duration.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题:提供与PLD接收机 - 发射机中使用的协议无关的速率协商。 解决方案:用于确定以时钟速率工作的可编程逻辑器件的串行接口通道中的数据速率的方法包括: 监视通道以发生单个位转换,并且基于在预定义的持续时间内检测到多个单个位转换,得出数据速率实际上是时钟速率的倍数。 版权所有(C)2009,JPO&INPIT

    Techniques for providing option conductors to connect components in oscillator circuit
    6.
    发明专利
    Techniques for providing option conductors to connect components in oscillator circuit 有权
    提供选择导体连接振荡器电路中组件的技术

    公开(公告)号:JP2013102456A

    公开(公告)日:2013-05-23

    申请号:JP2012275471

    申请日:2012-12-18

    Abstract: PROBLEM TO BE SOLVED: To provide techniques which allow use of option conductors to connect components in an oscillator circuit.SOLUTION: An oscillator circuit 200 includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes varactors 203 to 206, capacitors 221 to 226, and option conductors 207, 208, and 212 to 216 in a second conductive layer. The option conductors each form at least a portion of a connection between one of the transistors and one of a capacitor and a varactor. The oscillator circuit may further include an inductor coupled to one of a plurality of first transistors through the routing conductors in the first conductive layer, and a second option conductor in the second conductive layer that forms a first portion of the inductor.

    Abstract translation: 要解决的问题:提供允许使用选项导体连接振荡器电路中的组件的技术。 解决方案:振荡器电路200包括通过第一导电层中的布线导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的可变电抗器203至206,电容器221至226以及选项导体207,208和212至216。 选项导体各自形成晶体管之一和电容器和变容二极管之一之间的连接的至少一部分。 振荡器电路还可以包括通过第一导电层中的路由导体耦合到多个第一晶体管中的一个的电感器,以及形成电感器的第一部分的第二导电层中的第二选择导体。 版权所有(C)2013,JPO&INPIT

    Device and method for reducing pre-emphasis voltage jitter
    7.
    发明专利
    Device and method for reducing pre-emphasis voltage jitter 有权
    用于减少前置电压抖动器的装置和方法

    公开(公告)号:JP2012235468A

    公开(公告)日:2012-11-29

    申请号:JP2012104825

    申请日:2012-05-01

    CPC classification number: H04B3/06 H04L25/0272 H04L25/03343

    Abstract: PROBLEM TO BE SOLVED: To provide a transmitter circuit that reduces voltage jitter of data transmission.SOLUTION: A transmitter circuit comprises: a first current source; a first filter that is connected between the first current source and a first node; a second filter that is connected between the first current source and a second node; a second current source; a third filter that is connected between the second current source and a third node; a fourth filter that is connected between the second current source and a fourth node; a driver switch circuit that are connected to the first, second, third and fourth nodes; and the like.

    Abstract translation: 要解决的问题:提供减少数据传输的电压抖动的发射机电路。 解决方案:发射机电路包括:第一电流源; 连接在第一电流源和第一节点之间的第一滤波器; 连接在第一电流源和第二节点之间的第二滤波器; 第二个电流源; 连接在第二电流源和第三节点之间的第三滤波器; 连接在第二电流源和第四节点之间的第四滤波器; 驱动器开关电路,其连接到所述第一,第二,第三和第四节点; 等等。 版权所有(C)2013,JPO&INPIT

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