Abstract:
An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.
Abstract:
An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.
Abstract:
An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.
Abstract:
PROBLEM TO BE SOLVED: To provide high-speed serial digital data signal transmitter driver circuitry. SOLUTION: The present invention relates to transmitter driver circuitry for outputting a high-speed serial data signal having a serial bit rate in the range of about 10 Gbps, including H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor forming a portion of the H-tree driver circuitry further provides electrostatic discharge protection for the circuitry. COPYRIGHT: (C)2009,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a rate negotiation independent of a protocol in use in a PLD receiver-transmitter. SOLUTION: A method for determining a data rate in a serial interface channel for a programmable logic device operating at a clock rate includes; monitoring the channel for occurrence of a single bit transition, and concluding that the data rate is virtually a multiple of the clock rate based on detection of a plurality of single bit transitions in a predefined duration. COPYRIGHT: (C)2009,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide techniques which allow use of option conductors to connect components in an oscillator circuit.SOLUTION: An oscillator circuit 200 includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes varactors 203 to 206, capacitors 221 to 226, and option conductors 207, 208, and 212 to 216 in a second conductive layer. The option conductors each form at least a portion of a connection between one of the transistors and one of a capacitor and a varactor. The oscillator circuit may further include an inductor coupled to one of a plurality of first transistors through the routing conductors in the first conductive layer, and a second option conductor in the second conductive layer that forms a first portion of the inductor.
Abstract:
PROBLEM TO BE SOLVED: To provide a transmitter circuit that reduces voltage jitter of data transmission.SOLUTION: A transmitter circuit comprises: a first current source; a first filter that is connected between the first current source and a first node; a second filter that is connected between the first current source and a second node; a second current source; a third filter that is connected between the second current source and a third node; a fourth filter that is connected between the second current source and a fourth node; a driver switch circuit that are connected to the first, second, third and fourth nodes; and the like.