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    Programmable logic array integrated circuits
    3.
    发明专利
    Programmable logic array integrated circuits 未知

    公开(公告)号：GB2279790A

    公开(公告)日：1995-01-11

    申请号：GB9413678

    申请日：1994-07-07

    Applicant: ALTERA CORP

    Inventor： WATSON JAMES ,  MCCLINTOCK CAMERON ,  RANDHAWA HITEN ,  LI KEN ,  AHANIN BAHRAM

    IPC: H03K19/173 ,  H03K19/177

    Abstract: A programmable logic device comprises a global interconnect array 105 whose lines are fed via programmable multiplexer 110 to two stacks of logic array blocks (130 is one such block) on its sides. The logic array blocks include CMOS look up table based logic modules 260 that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.

    Expandable macrocell with reduced set-up time
    4.
    发明专利
    Expandable macrocell with reduced set-up time 未知

    公开(公告)号：GB2279830A

    公开(公告)日：1995-01-11

    申请号：GB9413399

    申请日：1994-07-04

    Applicant: ALTERA CORP

    Inventor： KIANI KUSHROW ,  BALICKI JANUSZ K ,  NOUBAN BEHZAD ,  LI KEN

    IPC: H03K19/173 ,  H03K19/177

    Abstract: A macrocell 100 for use in a programmable logic device (PLD) includes two reprogrammable look-up tables 102, 104 for increased fan-in, and two flip-flops 126, 128 that increases fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. The second register 126 can be used for receiving fast input signals 120 form an input to the PLD to reduce setup time. The allocation input and output lines allow cascading of macrocells. Programmable elements 108 - 124 may be implemented by RAM, EPROM, or fuse link memory cells.

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