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    Pld architecture for flexible arrangement of ip functional block
    1.
    发明专利
    Pld architecture for flexible arrangement of ip functional block 审中-公开
    IP功能块灵活布置的PLD架构

    公开(公告)号：JP2007081426A

    公开(公告)日：2007-03-29

    申请号：JP2006320925

    申请日：2006-11-28

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： LEE ANDY L ,  MCCLINTOCK CAMERON ,  BRIAN JOHNSON ,  CLIFF RICHARD ,  REDDY SRINIVAS ,  LANE CHRIS ,  LEVENTIS PAUL ,  BETZ VAUGHN TIMOTHY ,  LEWIS DAVID

    IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/177 ,  H03K19/17732 ,  H03K19/1778 ,  H03K19/17796

    Abstract: PROBLEM TO BE SOLVED: To provide a PLD architecture which allows an IP functional block to be arranged to optimize the routing architecture of base signals. SOLUTION: This programmable logical device (PLD) is provided with a plurality of logical elements(LEs) constituted into an array and the routing architecture of the base signals provided with a plurality of signal routing lines for routing signals among the LEs. A hole is formed inside the array of the LEs, the hole is featured by a peripheral part and a center part, the routing architecture of the base signals is at least partially interrupted at the hole, and the PLD is further provided with an interface circuit inside the peripheral part of the hole. The interface circuit can be constituted so that a circuit inside the hole is coupled to the architecture of routing the signals, and the PLD is further provided with the IP functional block inside the hole and is electrically coupled to the interface circuit. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种PLD架构，其允许IP功能块被布置成优化基本信号的路由架构。 解决方案：该可编程逻辑器件（PLD）被提供有构成阵列的多个逻辑元件（LE），并且基准信号的路由架构设置有用于在LE之间路由信号的多个信号路由线。 在LE的阵列内部形成一个孔，孔由周边部分和中心部分组成，基本信号的路由结构在孔处至少部分中断，并且PLD还具有接口电路 在孔的周边部分内。 接口电路可以构成为使得孔内的电路耦合到路由信号的架构，并且PLD还在孔内设置有IP功能块，并且电耦合到接口电路。 版权所有（C）2007，JPO＆INPIT

    Programmable logic array integrated circuits with interconnection conductors of overlapping extent
    4.
    发明专利
    Programmable logic array integrated circuits with interconnection conductors of overlapping extent 未知

    公开(公告)号：GB2300951B

    公开(公告)日：1999-07-07

    申请号：GB9610054

    申请日：1996-05-14

    Applicant: ALTERA CORP

    Inventor： LEONG WILLIAM ,  MCCLINTOCK CAMERON ,  CLIFF RICHARD G

    IPC: H03K19/177

    Abstract: A programmable logic array integrated circuit device has a plurality of programmable logic regions arranged in a two-dimensional array of intersecting rows and columns. Associated with each logic region in each row is a local feedback conductor that spans a unique plurality of other logic regions in the row. Each such local feedback conductor makes the output of the associated logic region available as a possible input to any of the logic regions spanned by that conductor. Each logic region also has several associated intermediary conductors for making the signals on longer leads (such as row-long leads) available as possible inputs to any of the logic regions spanned by the intermediary conductors. At least some of the intermediary conductors associated with each logic region span different groups of logic regions.

    Programmable logic array integrated circuits
    5.
    发明专利
    Programmable logic array integrated circuits 未知

    公开(公告)号：GB2279790A

    公开(公告)日：1995-01-11

    申请号：GB9413678

    申请日：1994-07-07

    Applicant: ALTERA CORP

    Inventor： WATSON JAMES ,  MCCLINTOCK CAMERON ,  RANDHAWA HITEN ,  LI KEN ,  AHANIN BAHRAM

    IPC: H03K19/173 ,  H03K19/177

    Abstract: A programmable logic device comprises a global interconnect array 105 whose lines are fed via programmable multiplexer 110 to two stacks of logic array blocks (130 is one such block) on its sides. The logic array blocks include CMOS look up table based logic modules 260 that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.

    Programmable logic array with overlapping interconnection conductors
    8.
    发明专利
    Programmable logic array with overlapping interconnection conductors 未知

    公开(公告)号：GB2300951A

    公开(公告)日：1996-11-20

    申请号：GB9610054

    申请日：1996-05-14

    Applicant: ALTERA CORP

    Inventor： LEONG WILLIAM ,  MCCLINTOCK CAMERON ,  CLIFF RICHARD G

    IPC: H03K19/177

    Abstract: A programmable logic array integrated circuit device has a plurality of programmable logic regions 20 arranged in a two-dimensional array of intersecting rows and columns. Associated with each logic region 20 in each row is a local feedback conductor 40 that spans a unique plurality of other logic regions in the row. Each such local feedback conductor 40 makes the output of the associated logic region 20 available as a possible input to any of the logic regions spanned by that conductor. Each logic region 20 also has several associated intermediary conductors 50 for making the signals on longer leads (such as row-long leads 70) available as possible inputs to any of the logic regions spanned by the intermediary conductors 50. At least some of the intermediary conductors associated with each logic region span different groups of logic regions.

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