公开(公告)号：WO0052824A9

公开(公告)日：2001-11-29

申请号：PCT/US0005483

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： PARK JIM ,  HUANG WEI-JEN ,  NGAI TONY ,  PEDERSON BRUCE A

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17792

Abstract: A programmable logic device is adapted to predict carry values in long-chain-carry logic configurations. In the most preferred embodiment, which functions in any long-carry-chain logic configuration, each logic region calculates a result for both values of the carry-in signal to that region, and when a carry signal for the group to which the region belongs reaches the region, the correct result in each region, and thece the correct carry-out for that group, are calculated and propagated. The carry-out terminal of one group is arranged to be adjacent to the carry-in terminal of the next group, to enhance carry propagation speed. In another embodiment, each region looks back two regions to predict the carry-in. In two additional embodiments, logic is provided to mathematically calculate the carry values.

Abstract translation: 可编程逻辑器件适用于预测长链进位逻辑配置中的进位值。 在最优选的实施例中，其在任何长承载链逻辑配置中起作用，每个逻辑区域计算对于该区域的进位信号的两个值的结果，以及当该区域所属的组的进位信号 到达区域，每个区域的正确结果，以及该组的正确执行情况都被计算和传播。 一组的进位终端被布置成与下一组的进位终端相邻，以提高进位传播速度。 在另一个实施例中，每个区域回顾两个区域以预测携带。 在两个附加实施例中，提供逻辑以在数学上计算进位值。