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    PROGRAMMABLE LOGIC DEVICE WITH CARRY-SELECT ADDITION
    1.
    发明申请
    PROGRAMMABLE LOGIC DEVICE WITH CARRY-SELECT ADDITION 审中-公开
    可编程逻辑器件与携带选择添加

    公开(公告)号：WO0052824A9

    公开(公告)日：2001-11-29

    申请号：PCT/US0005483

    申请日：2000-03-02

    Applicant: ALTERA CORP

    Inventor： PARK JIM ,  HUANG WEI-JEN ,  NGAI TONY ,  PEDERSON BRUCE A

    IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

    CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17792

    Abstract: A programmable logic device is adapted to predict carry values in long-chain-carry logic configurations. In the most preferred embodiment, which functions in any long-carry-chain logic configuration, each logic region calculates a result for both values of the carry-in signal to that region, and when a carry signal for the group to which the region belongs reaches the region, the correct result in each region, and thece the correct carry-out for that group, are calculated and propagated. The carry-out terminal of one group is arranged to be adjacent to the carry-in terminal of the next group, to enhance carry propagation speed. In another embodiment, each region looks back two regions to predict the carry-in. In two additional embodiments, logic is provided to mathematically calculate the carry values.

    Abstract translation: 可编程逻辑器件适用于预测长链进位逻辑配置中的进位值。 在最优选的实施例中，其在任何长承载链逻辑配置中起作用，每个逻辑区域计算对于该区域的进位信号的两个值的结果，以及当该区域所属的组的进位信号 到达区域，每个区域的正确结果，以及该组的正确执行情况都被计算和传播。 一组的进位终端被布置成与下一组的进位终端相邻，以提高进位传播速度。 在另一个实施例中，每个区域回顾两个区域以预测携带。 在两个附加实施例中，提供逻辑以在数学上计算进位值。

    INTERCONNECTION RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES
    2.
    发明申请
    INTERCONNECTION RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES 审中-公开
    可编程逻辑集成电路设备的互连资源

    公开(公告)号：WO0052825A9

    公开(公告)日：2001-11-29

    申请号：PCT/US0005488

    申请日：2000-03-02

    Applicant: ALTERA CORP

    Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

    IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

    CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

    INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES
    3.
    发明申请
    INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES 审中-公开
    用于可编程逻辑集成电路设备的互连和输入/输出资源

    公开(公告)号：WO0052826A2

    公开(公告)日：2000-09-08

    申请号：PCT/US0005628

    申请日：2000-03-02

    Applicant: ALTERA CORP

    Inventor： NGAI TONY ,  PEDERSON BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

    IPC: H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

    Abstract: A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

    Abstract translation: 可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

    5.
    发明专利
    未知

    公开(公告)号：DE60129269T2

    公开(公告)日：2008-04-17

    申请号：DE60129269

    申请日：2001-03-12

    Applicant: ALTERA CORP A DELAWARE CORP

    Inventor： NGAI TONY ,  PRASAD NITIN ,  TRAN THUNGOC

    IPC: G11C8/16 ,  G11C7/10 ,  G11C8/00 ,  G11C11/00 ,  H03K19/177

    Abstract: A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.

    Programmable logic with embedded memory blocks
    6.
    发明专利
    Programmable logic with embedded memory blocks 未知

    公开(公告)号：GB2351824A

    公开(公告)日：2001-01-10

    申请号：GB0016223

    申请日：2000-06-30

    Applicant: ALTERA CORP

    Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

    IPC: G11C5/02 ,  H03K19/177

    Abstract: A high-performance programmable logic architecture has embedded memory arranged at peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703,706) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements can be directly programmable routed and connected to driver blocks of the logic blocks in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources. Using similar direct programmable interconnections the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size

    Embedded memory blocks for programmable logic
    8.
    发明专利
    Embedded memory blocks for programmable logic 未知

    公开(公告)号：GB2391671A

    公开(公告)日：2004-02-11

    申请号：GB0324461

    申请日：2000-06-30

    Applicant: ALTERA CORP

    Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

    IPC: H03K19/177

    Abstract: A high-performance programmable logic architecture has embedded memory arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703,706) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements can be directly programmable routed and connected to driver blocks of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources. Using similar direct programmable interconnections the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources.

    Interconnection and input/output resources for programmable logic integrated circuit devices
    9.
    发明专利
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    用于可编程逻辑集成电路设备的互连和输入/输出资源

    公开(公告)号：JP2006287964A

    公开(公告)日：2006-10-19

    申请号：JP2006146009

    申请日：2006-05-25

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： NGAI TONY ,  PEDERSEN BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

    IPC: H03K19/177 ,  H01L21/82 ,  H03K19/173

    CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

    Abstract: PROBLEM TO BE SOLVED: To provide interconnection resources to be applied to a programmable logic device for accelerating an operating speed of a programmable logic array integrated circuit. SOLUTION: A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors) are provided for making programmable interconnection to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供应用于可编程逻辑器件的互连资源，以加速可编程逻辑阵列集成电路的工作速度。 解决方案：可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 互连资源（例如，互连导体）被提供用于对区域之间进行可编程的互连。 这些互连资源中的至少一些以架构上相似但具有显着不同的信号传播速度特性的两种形式提供。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 版权所有（C）2007，JPO＆INPIT

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