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    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
    2.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT 审中-公开
    静电放电保护电路

    公开(公告)号：WO2005122356A3

    公开(公告)日：2007-04-19

    申请号：PCT/US2005016101

    申请日：2005-05-06

    Applicant: ALTERA CORP ,  HUANG CHENG-HSIUNG ,  LIN GUU ,  LEE SHIH-LIN S ,  SHIH CHIH-CHING ,  RAHIM IRFAN ,  TRAN STEPHANIE T

    Inventor： HUANG CHENG-HSIUNG ,  LIN GUU ,  LEE SHIH-LIN S ,  SHIH CHIH-CHING ,  RAHIM IRFAN ,  TRAN STEPHANIE T

    IPC: H02H9/00 ,  H01L27/02

    CPC classification number: H01L27/0266 ,  H01L27/0251

    Abstract: Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses (56). Electrostatic discharge (ESD) protection circuitry (40) is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device (44) that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit (42) that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

    Abstract translation: 提供具有诸如可编程多晶硅保险丝（56）的敏感电路的集成电路。 提供静电放电（ESD）保护电路（40），其防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件（44），其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路（42），当电流跨越敏感电路施加最大电压时，该余量电路有助于防止电流流过敏感电路。

    4.
    发明专利
    未知

    公开(公告)号：AT422700T

    公开(公告)日：2009-02-15

    申请号：AT05767686

    申请日：2005-07-01

    Applicant: ALTERA CORP

    Inventor： SIDHU LAKHBEER S ,  RAHIM IRFAN ,  WATT JEFFREY ,  TURNER JOHN E

    IPC: G11C11/412

    Abstract: A configuration memory cell ("CRAM") for a field programmable gate array ("FPGA") integrated circuit ("IC") device is given increased resistance to single event upset ("SEU"). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

    5.
    发明专利
    未知

    公开(公告)号：DE602005012698D1

    公开(公告)日：2009-03-26

    申请号：DE602005012698

    申请日：2005-07-01

    Applicant: ALTERA CORP

    Inventor： SIDHU LAKHBEER S ,  RAHIM IRFAN ,  WATT JEFFREY ,  TURNER JOHN E

    IPC: G11C11/412

    Abstract: A configuration memory cell ("CRAM") for a field programmable gate array ("FPGA") integrated circuit ("IC") device is given increased resistance to single event upset ("SEU"). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

    Technique for combining volatile and non-volatile programmable logic on integrated circuit
    6.
    发明专利
    Technique for combining volatile and non-volatile programmable logic on integrated circuit 有权
    组合电路中挥发性和非易失性可编程逻辑的组合技术

    公开(公告)号：JP2006166430A

    公开(公告)日：2006-06-22

    申请号：JP2005336979

    申请日：2005-11-22

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： CAMAROTA RAFAEL ,  RAHIM IRFAN ,  ANG BOON JIN ,  CHONG THOW PANG

    IPC: H03K19/173

    CPC classification number: G06F15/7867 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17772 ,  H03K19/17776

    Abstract: PROBLEM TO BE SOLVED: To provide faster techniques for configuring field programmable gate arrays, and to provide ways to adequately secure user designs during the configuration process. SOLUTION: Volatile and non-volatile programmable logic are combined into one integrated circuit (IC). The IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供更快的技术来配置现场可编程门阵列，并提供在配置过程中充分保护用户设计的方法。 解决方案：易失性和非易失性可编程逻辑组合成一个集成电路（IC）。 IC分为两部分。 可编程逻辑的第一块由存储在片上非易失性存储器中的位来配置。 可编程逻辑的第二块由存储在片外存储器中的位配置。 IC上的IO组的功能在IC的两个逻辑块之间复用。 第一块中的可编程逻辑可以在可以配置第二块中的可编程逻辑的几分之一时间内完全起作用。 第一块中的可编程逻辑可以配置得足够快，并具有足够的独立性来辅助第二块的配置。 版权所有（C）2006，JPO＆NCIPI

    Configuration random access memory
    7.
    发明专利
    Configuration random access memory 审中-公开
    配置随机存取存储器

    公开(公告)号：JP2008176912A

    公开(公告)日：2008-07-31

    申请号：JP2008004824

    申请日：2008-01-11

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： RAHIM IRFAN ,  LEE ANDY L ,  WONG MYRON WAI ,  VEST WILLIAM BRADLEY ,  WATT JEFFREY T

    IPC: G11C11/41

    CPC classification number: H03K19/1776 ,  G11C11/401 ,  G11C11/404 ,  G11C14/00 ,  H03K19/1778

    Abstract: PROBLEM TO BE SOLVED: To provide an improved configuration random access memory. SOLUTION: A memory element has: an address transistor including a gate connected to an address line, a first source-drain connected to a data line and a second source-drain connected to a data node; a capacitor connected between a capacitor ground terminal and the second source-drain; and first and second cross-coupled inverters, the first inverter including an output connected to the data node and an input, and the second inverter including an input connected to the data node and an output. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种改进的配置随机存取存储器。 存储元件具有：地址晶体管，其包括连接到地址线的栅极，连接到数据线的第一源极 - 漏极和连接到数据节点的第二源极 - 漏极; 连接在电容器接地端子和第二源极 - 漏极之间的电容器; 以及第一和第二交叉耦合的反相器，所述第一反相器包括连接到所述数据节点的输出端和输入端，所述第二反相器包括连接到所述数据节点的输入端和输出端。 版权所有（C）2008，JPO＆INPIT

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