公开(公告)号：WO2006079073A3

公开(公告)日：2007-03-08

申请号：PCT/US2006002458

申请日：2006-01-24

Applicant: ALTERA CORP ,  WATT JEFFREY

Inventor： WATT JEFFREY

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.

Abstract translation: 用于提供用于模拟的网表的方法，软件和装置，其包括由一个或多个模式相关效应确定的一个或多个参数。 本发明的一个具体实施例接收包括一个或多个MOSFET晶体管的电路的布局。 对于一个或多个MOSFET晶体管，使用接收的布局测量晶体管之间的间隔，并且确定模式相关参数。 该参数修改模拟中使用的门的长度。 在其他实施例中，可以使用其他模式相关效应来确定一个或多个参数的值。 这些参数可用于修改栅极长度，发射极尺寸，电阻器宽度或其他器件特性。

公开(公告)号：AT422700T

公开(公告)日：2009-02-15

申请号：AT05767686

申请日：2005-07-01

Applicant: ALTERA CORP

Inventor： SIDHU LAKHBEER S ,  RAHIM IRFAN ,  WATT JEFFREY ,  TURNER JOHN E

IPC: G11C11/412

Abstract: A configuration memory cell ("CRAM") for a field programmable gate array ("FPGA") integrated circuit ("IC") device is given increased resistance to single event upset ("SEU"). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

公开(公告)号：DE602005012698D1

公开(公告)日：2009-03-26

申请号：DE602005012698

申请日：2005-07-01

Applicant: ALTERA CORP

Inventor： SIDHU LAKHBEER S ,  RAHIM IRFAN ,  WATT JEFFREY ,  TURNER JOHN E

IPC: G11C11/412

Abstract: A configuration memory cell ("CRAM") for a field programmable gate array ("FPGA") integrated circuit ("IC") device is given increased resistance to single event upset ("SEU"). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

公开(公告)号：JP2007053761A

公开(公告)日：2007-03-01

申请号：JP2006221341

申请日：2006-08-15

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： LEWIS DAVID ,  BETZ VAUGHN ,  LEVENTIS PAUL ,  CHRISTOPHER LANE ,  LEE ANDY ,  WATT JEFFREY ,  VANDERHOEK TIMOTHY

IPC: H03K19/173 ,  G06F17/50 ,  H01L21/82

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  H03K19/17784

Abstract: PROBLEM TO BE SOLVED: To optimize the power consumption of a programmable logic device (PLD) and to obtain optimum levels of the power consumption and PLD operation speed. SOLUTION: The PLD (103) includes first and second circuits. The first and second circuits are portions of user design implemented by using resources of the PLD. The first circuit is powered with a first supply voltage. The second circuit is powered with a second supply voltage. At least one of the first and second supply voltages is determined by a computer-aided design (CAD) flow of the PLD used to implement the user design in the PLD. Further, the first and second supply voltages are supplied by an external regulator (303) of the PLD. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：优化可编程逻辑器件（PLD）的功耗，并获得功耗和PLD操作速度的最佳水平。 解决方案：PLD（103）包括第一和第二电路。 第一和第二电路是通过使用PLD的资源实现的用户设计的部分。 第一个电路由第一个电源供电。 第二个电路由第二个电源供电。 第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD的计算机辅助设计（CAD）流程确定。 此外，第一和第二电源电压由PLD的外部调节器（303）提供。 版权所有（C）2007，JPO＆INPIT