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    Programmable logic device with stabilizing configuration cell for reducing soft error
    1.
    发明专利
    Programmable logic device with stabilizing configuration cell for reducing soft error 审中-公开
    具有稳定配置单元的可编程逻辑器件，用于减少软错误

    公开(公告)号：JP2005039210A

    公开(公告)日：2005-02-10

    申请号：JP2004138377

    申请日：2004-05-07

    Applicant: Altera Corp ,  アルテラ・コーポレーション

    Inventor： TURNER JOHN E

    IPC: H01L27/04 ,  G11C11/412 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

    CPC classification number: G11C11/4125

    Abstract: PROBLEM TO BE SOLVED: To provide a method reducing soft error rates by stabilizing a configuration memory cell in a programmable logic device.
    SOLUTION: The configuration memory cell in the programmable logic device comprises: a pair of cross-coupling inverters, connected between the input terminal of a programmable logic device memory cell and the output terminal thereof, which store programming data; and a stabilizing capacitor connected between the input terminal of the configuration memory cell in the programmable logic device and the output terminal of the programmable logic device memory cell. This stabilizing capacitor acts so that a voltage on the input terminal of the configuration memory cell in the programmable logic device and the output terminal of the configuration memory cell in the programmable logic device is buffered when the memory cell breaks a radiation.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：通过稳定可编程逻辑器件中的配置存储单元来提供降低软错误率的方法。 解决方案：可编程逻辑器件中的配置存储单元包括：一对交叉耦合反相器，连接在可编程逻辑器件存储单元的输入端和其输出端之间，存储编程数据; 以及稳定电容器，其连接在可编程逻辑器件中的配置存储单元的输入端子与可编程逻辑器件存储单元的输出端子之间。 该稳定电容器用于当存储器单元断开辐射时缓冲可编程逻辑器件中的配置存储单元的输入端上的电压和可编程逻辑器件中的配置存储单元的输出端子上的电压。 版权所有（C）2005，JPO＆NCIPI

    An IC with I/O configurable for coupling to different operating voltage environments
    2.
    发明专利
    An IC with I/O configurable for coupling to different operating voltage environments 未知

    公开(公告)号：GB2313968A

    公开(公告)日：1997-12-10

    申请号：GB9710966

    申请日：1997-05-28

    Applicant: ALTERA CORP

    Inventor： WONG WILSON ,  PATEL RAKESH H ,  TURNER JOHN E ,  LAM JOHN D

    IPC: H01L27/04 ,  G11C5/14 ,  H01L21/822 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

    Abstract: The core of an IC may be supplied with a reduced voltage by an internal voltage dropping circuit VDC, while the input and output circuits remain compatible with circuits supplied with an unreduced voltage. Alternatively, the IC may be supplied with reduced voltage, and the input can be configured to accept signals from circuits supplied with the reduced voltage (figure 4), or from circuits supplied with the unreduced voltage (figure 5). When the IC is supplied with reduced voltage, an output driver (figure 9a) may be protected against leakage currents by applying a boosted voltage, e.g. from a voltage pump, to some driver nodes. The same IC design may be used in different operating modes depending on the option selected by metal masks, by fuses, or by EEPROM, EPROM, or SRAM cells.

    A programmable interconnect junction
    4.
    发明专利
    A programmable interconnect junction 未知

    公开(公告)号：GB2312068A

    公开(公告)日：1997-10-15

    申请号：GB9707323

    申请日：1997-04-10

    Applicant: ALTERA CORP

    Inventor： PASS CHRISTOPHER J ,  SANSBURY JAMES D ,  MADURAWE RAMINDA U ,  TURNER JOHN E ,  PATEL RAKESH H ,  WRIGHT PETER J

    IPC: H03K19/177 ,  H03K19/0175

    Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line. An interconnect transistor 610 and a memory transistor 635 share a floating gate 620 which is charged via a write transistor 650 and tunnel diode 660 and controlled from a line 670 via a capacitor 680. A read transistor 630 can be used for margin testing.

    5.
    发明专利
    未知

    公开(公告)号：AT422700T

    公开(公告)日：2009-02-15

    申请号：AT05767686

    申请日：2005-07-01

    Applicant: ALTERA CORP

    Inventor： SIDHU LAKHBEER S ,  RAHIM IRFAN ,  WATT JEFFREY ,  TURNER JOHN E

    IPC: G11C11/412

    Abstract: A configuration memory cell ("CRAM") for a field programmable gate array ("FPGA") integrated circuit ("IC") device is given increased resistance to single event upset ("SEU"). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

    9.
    发明专利
    未知

    公开(公告)号：DE602005012698D1

    公开(公告)日：2009-03-26

    申请号：DE602005012698

    申请日：2005-07-01

    Applicant: ALTERA CORP

    Inventor： SIDHU LAKHBEER S ,  RAHIM IRFAN ,  WATT JEFFREY ,  TURNER JOHN E

    IPC: G11C11/412

    Abstract: A configuration memory cell ("CRAM") for a field programmable gate array ("FPGA") integrated circuit ("IC") device is given increased resistance to single event upset ("SEU"). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

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