公开(公告)号：WO2010014355A3

公开(公告)日：2010-04-08

申请号：PCT/US2009049713

申请日：2009-07-06

Applicant: ALTERA CORP ,  RATNAKUMAR ALBERT ,  XIANG QI ,  TUNG JEFFREY XIAOQI

Inventor： RATNAKUMAR ALBERT ,  XIANG QI ,  TUNG JEFFREY XIAOQI

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L29/94

Abstract: A varactor may have a first terminal connected to a gate. The gate may be formed from a p-type polysilicon gate conductor. The gate may also have a gate insulator formed from a layer of insulator such as silicon oxide. The gate insulator may be located between the gate conductor and a body region. Source and drain contact regions may be formed in a silicon body region. The body region and the source and drain may be doped with n-type dopant. The varactor may have a second terminal connected to the n-type source and drain. A control voltage may be used to adjust the level of capacitance produced by the varactor between the first and second terminals. A positive control voltage may produce a larger capacitance than a negative control voltage. Application of the negative control voltage may produce a depletion layer in the p+ polysilicon gate layer.

Abstract translation: 变容二极管可以具有连接到门的第一端子。 栅极可以由p型多晶硅栅极导体形成。 栅极还可以具有由诸如氧化硅的绝缘体层形成的栅极绝缘体。 栅极绝缘体可以位于栅极导体与本体区域之间。 源极和漏极接触区域可以形成在硅本体区域中。 体区和源极和漏极可以掺杂有n型掺杂剂。 变容管可以具有连接到n型源极和漏极的第二端子。 可以使用控制电压来调整由第一和第二端子之间的变容二极管产生的电容的电平。 正控制电压可能产生比负控制电压更大的电容。 施加负控制电压可能在p +多晶硅栅极层中产生耗尽层。

公开(公告)号：WO2010042542A3

公开(公告)日：2010-07-15

申请号：PCT/US2009059729

申请日：2009-10-06

Applicant: ALTERA CORP ,  SARDANA CHARU ,  RATNAKUMAR ALBERT ,  JENSEN BRADLEY ,  WATT JEFFREY T

Inventor： SARDANA CHARU ,  RATNAKUMAR ALBERT ,  JENSEN BRADLEY ,  WATT JEFFREY T

IPC: H01L27/108 ,  H01L27/04

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-oxide-metal capacitors with bar vias are provided for integrated circuits. The capacitors may be formed in the interconnect layers of integrated circuits. Stacked bar vias and metal lines in the interconnect layers may be connected to form conductive vertical plates that span multiple interconnect layers. The capacitors with bar vias may be formed by placing multiple vertical plates formed from stacked bar vias and metal lines parallel to each other, alternating the polarity of adjacent vertical parallel plates to form multiple parallel plate capacitors. The parallel plates may be interconnected to form first and second terminals in a capacitor.

Abstract translation: 为集成电路提供带条形过孔的金属氧化物金属电容器。 电容器可以形成在集成电路的互连层中。 互连层中的堆叠条形过孔和金属线可以连接以形成跨越多个互连层的导电垂直板。 具有条形过孔的电容器可以通过放置由堆叠条形过孔和金属线形成的多个垂直板彼此平行，交替相邻垂直平行板的极性以形成多个平行板电容器来形成。 平行板可以互连以形成电容器中的第一和第二端子。

公开(公告)号：WO2010039444A2

公开(公告)日：2010-04-08

申请号：PCT/US2009057271

申请日：2009-09-17

Applicant: ALTERA CORP ,  XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

Inventor： XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

IPC: H01L27/088 ,  H01L21/265

CPC classification number: G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

Abstract translation: 提出了一种使用正向偏置和改进的混合信号处理的电路设计来提高模拟电路性能的方法。 定义了由多个NMOS和PMOS晶体管组成的电路。 NMOS晶体管的体端耦合到第一电压源并且PMOS晶体管的体端耦合到第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的本体端子并且将第二电压源施加到每个选定的PMOS晶体管的本体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的本体端子提供正向和反向偏置。

公开(公告)号：EP2342749A4

公开(公告)日：2012-10-17

申请号：EP09818220

申请日：2009-09-17

Applicant: ALTERA CORP

Inventor： XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

IPC: H01L27/088 ,  G05F3/20 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833