公开(公告)号：WO2010014355A3

公开(公告)日：2010-04-08

申请号：PCT/US2009049713

申请日：2009-07-06

Applicant: ALTERA CORP ,  RATNAKUMAR ALBERT ,  XIANG QI ,  TUNG JEFFREY XIAOQI

Inventor： RATNAKUMAR ALBERT ,  XIANG QI ,  TUNG JEFFREY XIAOQI

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L29/94

Abstract: A varactor may have a first terminal connected to a gate. The gate may be formed from a p-type polysilicon gate conductor. The gate may also have a gate insulator formed from a layer of insulator such as silicon oxide. The gate insulator may be located between the gate conductor and a body region. Source and drain contact regions may be formed in a silicon body region. The body region and the source and drain may be doped with n-type dopant. The varactor may have a second terminal connected to the n-type source and drain. A control voltage may be used to adjust the level of capacitance produced by the varactor between the first and second terminals. A positive control voltage may produce a larger capacitance than a negative control voltage. Application of the negative control voltage may produce a depletion layer in the p+ polysilicon gate layer.

Abstract translation: 变容二极管可以具有连接到门的第一端子。 栅极可以由p型多晶硅栅极导体形成。 栅极还可以具有由诸如氧化硅的绝缘体层形成的栅极绝缘体。 栅极绝缘体可以位于栅极导体与本体区域之间。 源极和漏极接触区域可以形成在硅本体区域中。 体区和源极和漏极可以掺杂有n型掺杂剂。 变容管可以具有连接到n型源极和漏极的第二端子。 可以使用控制电压来调整由第一和第二端子之间的变容二极管产生的电容的电平。 正控制电压可能产生比负控制电压更大的电容。 施加负控制电压可能在p +多晶硅栅极层中产生耗尽层。

公开(公告)号：WO2010039444A2

公开(公告)日：2010-04-08

申请号：PCT/US2009057271

申请日：2009-09-17

Applicant: ALTERA CORP ,  XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

Inventor： XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

IPC: H01L27/088 ,  H01L21/265

CPC classification number: G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

Abstract translation: 提出了一种使用正向偏置和改进的混合信号处理的电路设计来提高模拟电路性能的方法。 定义了由多个NMOS和PMOS晶体管组成的电路。 NMOS晶体管的体端耦合到第一电压源并且PMOS晶体管的体端耦合到第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的本体端子并且将第二电压源施加到每个选定的PMOS晶体管的本体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的本体端子提供正向和反向偏置。

公开(公告)号：JP2012199545A

公开(公告)日：2012-10-18

申请号：JP2012056840

申请日：2012-03-14

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： ALBERT RATNAKUMAR ,  XIANG QI ,  MAANGAT SIMARDEEP ,  JUN LIU

IPC: H01L27/04 ,  G05F3/30 ,  H01L21/329 ,  H01L21/822 ,  H01L29/88 ,  H01L29/94

CPC classification number: G05F3/30

Abstract: PROBLEM TO BE SOLVED: To provide a reference circuit which operates with a low voltage.SOLUTION: A low-voltage reference circuit can comprise a pair of semiconductor devices. Each of the semiconductor devices can include an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator. The gate insulator is inserted between the metal gate and the n-type semiconductor region, and carriers tunnel through the metal gate and the n-type semiconductor region. The metal gate can have a work function which matches a work function of a p-type polysilicon. The gate insulator can have a thickness smaller than approximately 25 angstroms. The metal gate can form a first terminal in the semiconductor device. The n+ region and the n-type semiconductor region can form a second terminal in the semiconductor device. The second terminal can be coupled to the ground. A bias circuit can use the first terminal so as to supply a different current to the semiconductor device, and can supply a corresponding reference output voltage at a value less than 1 volt.

Abstract translation: 要解决的问题：提供以低电压工作的参考电路。 解决方案：低压参考电路可以包括一对半导体器件。 每个半导体器件可以包括n型半导体区域，n型半导体区域中的n +区域，金属栅极和栅极绝缘体。 栅极绝缘体插入在金属栅极和n型半导体区域之间，并且载流子穿过金属栅极和n型半导体区域。 金属栅极可以具有匹配p型多晶硅的功函数的功函数。 栅极绝缘体可以具有小于约25埃的厚度。 金属栅极可以在半导体器件中形成第一端子。 n +区域和n型半导体区域可以在半导体器件中形成第二端子。 第二个终端可以耦合到地面。 偏置电路可以使用第一端子以向半导体器件提供不同的电流，并且可以以小于1伏的值提供相应的参考输出电压。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：EP2342749A4

公开(公告)日：2012-10-17

申请号：EP09818220

申请日：2009-09-17

Applicant: ALTERA CORP

Inventor： XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

IPC: H01L27/088 ,  G05F3/20 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833