公开(公告)号：AT456882T

公开(公告)日：2010-02-15

申请号：AT06005634

申请日：2006-03-20

Applicant: ALTERA CORP

Inventor： VENKATA RAMANAND ,  LEE CHONG H ,  PATEL RAKESH H

IPC: H03K19/177

Abstract: A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

公开(公告)号：DE602006011974D1

公开(公告)日：2010-03-18

申请号：DE602006011974

申请日：2006-03-20

Applicant: ALTERA CORP

Inventor： VENKATA RAMANAND ,  LEE CHONG H ,  PATEL RAKESH H

IPC: H03K19/177

Abstract: A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

公开(公告)号：DE602004009620D1

公开(公告)日：2007-12-06

申请号：DE602004009620

申请日：2004-01-20

Applicant: ALTERA CORP

Inventor： VENKATA RAMANAND ,  LEE CHONG H ,  LUI HENRY

IPC: H03L7/081 ,  G01R25/00 ,  H03L7/08 ,  H03L7/089 ,  H04L7/033

Abstract: Phase locked loop circuitry (150) operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals (154) the signal that is closest in phase to transitions in another signal (152) such as a clock data recovery ("CDR") signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal.

公开(公告)号：JP2007028614A

公开(公告)日：2007-02-01

申请号：JP2006190911

申请日：2006-07-11

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： TRAN THUNGOC ,  SHUMARAYEV SERGEY Y ,  HOANG TIM TRI ,  XUE NING ,  LEE CHONG ,  VENKATA RAMANAND

IPC: H03K19/173 ,  H04J99/00

CPC classification number: H03K19/17736 ,  H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To reduce a downstream network load due to synchronization generated between the outputs of a four channel system, when four or more channels operate simultaneously. SOLUTION: The integrated circuit such as a programmable logic device (PLD) or the like includes multiple channels (30-0 to 30-3) of data communications circuitry. Circuitry is (54, 60) provided between these channels which are grouped in various sizes so as to selectively share signals. Thus, the device can appropriately support a communication protocol requesting various numbers of channels. The shared signals can include a clock signal, or an FIFO writing/reading permission signal. The circuit is preferably arranged in modules (that is, a certain channel and adjacent channels thereof, and/or a channel in a certain group and channels in neighboring groups thereof are equivalent or substantially equivalent) for facilitating the circuit design, circuit checking or the like. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：当四个或更多个信道同时工作时，由于四通道系统的输出之间产生的同步而减少下游网络负载。 解决方案：诸如可编程逻辑器件（PLD）等的集成电路包括数据通信电路的多个通道（30-0至30-3）。 在这些通道之间提供电路（54,60），其被分组成各种尺寸以便选择性地共享信号。 因此，设备可以适当地支持请求各种信道数量的通信协议。 共享信号可以包括时钟信号或FIFO写入/读取许可信号。 电路优选地布置在模块中（即，某个信道及其相邻信道，和/或某个组中的信道，并且相邻组中的信道相当于或基本相等），以便于电路设计，电路检查或 喜欢。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007018498A

公开(公告)日：2007-01-25

申请号：JP2006086647

申请日：2006-03-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： VENKATA RAMANAND ,  PATEL RAKESH H ,  LEE CHONG H

IPC: G06F13/38 ,  G06F3/00 ,  H04L13/08 ,  H04L29/08

CPC classification number: H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide a serial interface capable of responding suitably to a wide range data rate. SOLUTION: A serial interface for a PLD (20) supports a wide range of the data rate by providing the first number of channels (21-24) for supporting the data rate of the first range and the second number of channels (200) for supporting the second range of the data rate. The data rate for the first range is lower than the data rate for the second range. The first number of the channels is larger than the number of the second channels which is preferably one. The number of the first channels in each of the interfaces is suitably four. Each of the channels includes a physical medium connection module (26) and a physically coded sublayer module (25). Each of the high-speed channels for the channels of the second number includes a clock management unit. The low-speed channel of the channel of the first number shares one or more clock management units. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供能够适应于宽范围数据速率的串行接口。 解决方案：PLD（20）的串行接口通过提供第一数量的通道（21-24）来支持宽范围的数据速率，用于支持第一范围和第二数量通道的数据速率 200）用于支持数据速率的第二范围。 第一范围的数据速率低于第二范围的数据速率。 通道的第一数量大于最好是一个的第二通道的数量。 每个接口中的第一个通道的数量适当地为4个。 每个通道包括物理介质连接模块（26）和物理编码子层模块（25）。 用于第二号码的频道的每个高速频道包括时钟管理单元。 第一个频道的低速频道共享一个或多个时钟管理单元。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007043716A

公开(公告)日：2007-02-15

申请号：JP2006211485

申请日：2006-08-02

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGUYEN TOAN THANH ,  TRAN THUNGOC ,  SHUMARAYEV SERGEY Y ,  ZALIZNYAK ARCH ,  WANG SHOUJUN ,  VENKATA RAMANAND ,  LEE CHONG

IPC: H03K19/173

CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

Abstract: PROBLEM TO BE SOLVED: To provide serializer circuitry for executing serializing of parallel data at a data speed over a wide range under many different communication protocols. SOLUTION: The serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device ("PLD") or the like includes circuitry 10 for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects and at least some of the configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD). COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供串行器电路，用于在许多不同的通信协议下以宽范围的数据速度执行并行数据的串行化。 解决方案：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路10。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，并且可以动态地控制至少一些配置/重新配置（即在PLD的用户模式操作期间）。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007043718A

公开(公告)日：2007-02-15

申请号：JP2006211487

申请日：2006-08-02

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： NGUYEN TOAN THANH ,  TRAN THUNGOC ,  SHUMARAYEV SERGEY Y ,  ZALIZNYAK ARCH ,  HOANG TIM T ,  VENKATA RAMANAND ,  LEE CHONG

IPC: H03K19/173 ,  H03K17/00

CPC classification number: H03M9/00

Abstract: PROBLEM TO BE SOLVED: To provide a deserializer circuitry that can convert data of a serial form into data of a parallel form for a number of different communication protocols and over a wide range of possible data rates.
SOLUTION: The deserializer circuitry (10) for high-speed serial data receiver circuitry on a programmable logic device ("PLD") or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry (10) can also operate at any frequency in a wide range of frequencies. The circuitry (10) is configurable/re-configurable in various respects and at least some of the configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种解串器电路，其可以将串行形式的数据转换为多种不同通信协议的并行形式的数据，并且可以在宽范围的可能数据速率下进行。 解决方案：用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串行器电路（10）包括用于将串行数据转换成具有几个数据宽度中的任一个的并行数据的电路。 电路（10）还可以在宽频率范围内的任何频率下工作。 电路（10）可以在各个方面进行配置/重新配置，并且至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006302277A

公开(公告)日：2006-11-02

申请号：JP2006107956

申请日：2006-04-10

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： VENKATA RAMANAND ,  LEE CHONG H ,  PATEL RAKESH H

IPC: G06F13/38 ,  H03K19/173

CPC classification number: H03K19/17744

Abstract: PROBLEM TO BE SOLVED: To provide a high-speed serial interface offering a wide-range data rate.
SOLUTION: This serial interface for the programmable logic device can work according to various communication protocols and includes a receiver part (350) and a transmitter part (370). The receiver part is provided with a word alignment step or a byte alignment step (321), a deskew step (322), a rate compensation step or a rate matching step (323), an embedded protocol decoder step (324), a byte serial-parallel converter step (325), a byte rearrangement step (326), and a phase compensation step (327) at least. The transmitter part includes a phase compensation step (371), a byte parallel/serial converter step (372), and an embedded protocol encoder step (373) at least. Each of the steps may have a plurality of associated circuits. A selection circuit (for example, a multiplexer) selects a proper step and a circuit in each step as to a protocol to be used.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供提供广泛数据速率的高速串行接口。 解决方案：用于可编程逻辑器件的该串行接口可以根据各种通信协议工作，并且包括接收器部分（350）和发射器部分（370）。 接收器部分设置有字对准步骤或字节对准步骤（321），偏移校正步骤（322），速率补偿步骤或速率匹配步骤（323），嵌入式协议解码器步骤（324），字节 串行并行转换器步骤（325），字节重排步骤（326）和相位补偿步骤（327）。 发射机部分至少包括相位补偿步骤（371），字节并行/串行转换器步骤（372）和嵌入式协议编码器步骤（373）。 每个步骤可以具有多个相关电路。 选择电路（例如，多路复用器）对于要使用的协议在每个步骤中选择适当的步骤和电路。 版权所有（C）2007，JPO＆INPIT