公开(公告)号：WO2014182393A1

公开(公告)日：2014-11-13

申请号：PCT/US2014/032811

申请日：2014-04-03

Applicant: APPLE INC.

Inventor： SUKALPA, Biswas ,  SHIU, Shinye ,  DE LA CROPTE DE CHANTERAC, Cyril ,  GULATI, Manu ,  DESAI, Pulkit ,  HU, Rong Zhang

IPC: G06F3/14 ,  G09G5/393 ,  G09G5/395 ,  G09G5/00

CPC classification number: G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。

公开(公告)号：WO2010093868A1

公开(公告)日：2010-08-19

申请号：PCT/US2010/024021

申请日：2010-02-12

Applicant: APPLE INC. ,  SHIU, Shinye ,  LILLY, Brian P.

Inventor： SHIU, Shinye ,  LILLY, Brian P.

IPC: H03K17/693

CPC classification number: G11C8/12 ,  G06F12/0846 ,  G11C5/025 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1075 ,  G11C8/16 ,  G11C2207/108 ,  Y02D10/13

Abstract: An integrated circuit. The integrated circuit includes a plurality of memory requestors and a memory supercell. The memory supercell includes a plurality of memory banks each of which forms a respective range of separately addressable storage locations, wherein the memory supercell is organized into a plurality of bank groups. Each of the plurality of bank groups includes a subset of the plurality of memory banks and a corresponding dedicated access port. The integrated circuit further includes a switch coupled between the plurality of memory requestors and the memory supercell. The switch is configured, responsive to a memory request by a given one of the plurality of memory requestors, to connect a data path between the given memory requestor and the dedicated access port of a particular one of the bank groups addressed by the memory request.

Abstract translation: 集成电路。 集成电路包括多个存储器请求器和存储器超单元。 存储器超信元包括多个存储器组，每个存储器组分别形成分别可寻址存储位置的相应范围，其中存储器超级单元被组织成多个存储体组。 多个存储体组中的每一个包括多个存储器组的子集和相应的专用存取端口。 集成电路还包括耦合在多个存储器请求器和存储器超单元之间的开关。 响应于多个存储器请求器中给定的一个存储器请求器的存储器请求来配置该开关以连接给定存储器请求器与由存储器请求寻址的特定一个存储体组的专用存取端口之间的数据路径。

公开(公告)号：WO2014172078A1

公开(公告)日：2014-10-23

申请号：PCT/US2014/031699

申请日：2014-03-25

Applicant: APPLE INC.

Inventor： BISWAS, Sukalpa ,  KLINGAUF, Wolfgang H. ,  HU, Rong Zhang ,  SHIU, Shinye

IPC: G06F12/08 ,  G09G5/395 ,  G06F1/32

CPC classification number: G06F12/0871 ,  G06F1/3218 ,  G06F1/3275 ,  G06F12/0864 ,  G06F12/0893 ,  G06F12/122 ,  G06F2212/1028 ,  G06F2212/171 ,  G06F2212/6046 ,  G09G5/395 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2360/121 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods and systems for cache allocation schemes optimized for browsing applications. A memory controller includes a memory cache for reducing the number of requests that access off-chip memory. When an idle screen use case is detected, the frame buffer is allocated to the memory cache using a sequential allocation mode. Pixels are allocated to indexes of a given way in a sequential fashion, and then each way is accessed in a sequential fashion. When a given way is being accessed, the other ways of the memory cache are put into retention mode to reduce the leakage power.

Abstract translation: 针对浏览应用程序优化的缓存分配方案的方法和系统。 存储器控制器包括用于减少访问片外存储器的请求数量的存储器高速缓存。 当检测到空闲屏幕用例时，使用顺序分配模式将帧缓冲区分配给存储器高速缓存。 以顺序方式将像素分配给给定方式的索引，然后以顺序的方式访问各种方式。 当访问给定的方式时，存储器高速缓存的其他方式进入保留模式以减少泄漏功率。

公开(公告)号：WO2014052589A2

公开(公告)日：2014-04-03

申请号：PCT/US2013/061919

申请日：2013-09-26

Applicant: APPLE INC.

Inventor： BISWAS, Sukalpa ,  SHIU, Shinye ,  WANG, James ,  HU, Robert

IPC: G06F12/08

CPC classification number: G06F12/126 ,  G06F1/3225 ,  G06F12/0842

Abstract: Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID.

Abstract translation: 用于释放一个或多个组ID的高速缓存行粘性状态的方法和设备。 粘性删除引擎遍历系统缓存的标签内存，寻找与第一组ID相匹配的第一组ID，该ID将从系统缓存中清除其缓存行。 引擎清除属于第一组ID的每个缓存行的粘滞状态。 如果引擎收到第二组ID的释放请求，则引擎会记录当前索引以通过标签内存记录其进度。 然后，引擎继续浏览标签内存，查找与第一组或第二组ID相匹配的内容。 引擎回卷到标签内存的开始位置，继续走路，直到达到第二组ID的已记录索引。

公开(公告)号：WO2014052383A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/061572

申请日：2013-09-25

Applicant: APPLE INC.

Inventor： BISWAS, Sukalpa ,  SHIU, Shinye ,  KELLER, James B.

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0859 ,  G06F12/126 ,  Y02D10/13

Abstract: Methods and apparatuses for utilizing a data pending state for cache misses in a system cache. To reduce the size of a miss queue that is searched by subsequent misses, a cache line storage location is allocated in the system cache for a miss and the state of the cache line storage location is set to data pending. A subsequent request that hits to the cache line storage location will detect the data pending state and as a result, the subsequent request will be sent to a replay buffer. When the fill for the original miss comes back from external memory, the state of the cache line storage location is updated to a clean state. Then, the request stored in the replay buffer is reactivated and allowed to complete its access to the cache line storage location.

Abstract translation: 用于在系统高速缓存中利用数据挂起状态用于高速缓存未命中的方法和装置。 为了减少由后续未命中搜索的未命中队列的大小，高速缓存行存储位置在系统高速缓存中被分配为未命中，并且高速缓存行存储位置的状态被设置为数据挂起。 命中缓存行存储位置的后续请求将检测数据待处理状态，结果将后续请求发送到重放缓冲区。 当原始错误的填充从外部存储器返回时，缓存行存储位置的状态被更新为干净状态。 然后，重新启动存储在重放缓冲区中的请求，并允许其完成对高速缓存行存储位置的访问。

公开(公告)号：EP2387786A1

公开(公告)日：2011-11-23

申请号：EP10700790.8

申请日：2010-01-15

Applicant: Apple Inc.

Inventor： SHIU, Shinye ,  VON KAENEL, Vincent, R.

IPC: G11C5/14 ,  G11C11/413

CPC classification number: G11C11/413

Abstract: A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a voltage supply node, and a comparator may be coupled to compare a voltage level present on the virtual voltage rail to a reference voltage to thereby provide an output signal based on the comparison. The switching circuit may be configured to electrically couple the virtual voltage rail to the voltage supply node depending upon the output signal. In some embodiments, the switching circuit may be implemented using either a PMOS transistor or an NMOS transistor, although other embodiments may employ other switching circuits.

公开(公告)号：EP2901287A2

公开(公告)日：2015-08-05

申请号：EP13774572.5

申请日：2013-09-26

Applicant: Apple Inc.

Inventor： BISWAS, Sukalpa ,  SHIU, Shinye ,  WANG, James ,  HU, Robert

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/126 ,  G06F1/3225 ,  G06F12/0842

Abstract: Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID.

Abstract translation: 用于释放用于一个或多个组ID的高速缓存行的粘性状态的方法和装置。 粘性移除引擎遍历系统缓存的标签存储器，寻找与从系统高速缓存清除其高速缓存行的第一组ID的匹配。 引擎清除属于第一组ID的每条缓存线的粘性状态。 如果引擎接收到第二组ID的释放请求，则引擎记录当前索引以通过标记存储器记录其进度。 然后，引擎继续穿过标签内存，寻找与第一或第二组ID的匹配。 发动机绕包到标签存储器的开头，并继续其行进直到到达第二组ID的记录索引。

公开(公告)号：EP2387786B1

公开(公告)日：2015-04-22

申请号：EP10700790.8

申请日：2010-01-15

Applicant: Apple Inc.

Inventor： SHIU, Shinye ,  VON KAENEL, Vincent, R.

IPC: G11C5/14 ,  G11C11/413

CPC classification number: G11C11/413

公开(公告)号：WO2010083411A1

公开(公告)日：2010-07-22

申请号：PCT/US2010/021191

申请日：2010-01-15

Applicant: APPLE INC. ,  SHIU, Shinye ,  VON KAENEL, Vincent, R.

Inventor： SHIU, Shinye ,  VON KAENEL, Vincent, R.

IPC: G11C5/14 ,  G11C11/413

CPC classification number: G11C11/413

Abstract: A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a voltage supply node, and a comparator may be coupled to compare a voltage level present on the virtual voltage rail to a reference voltage to thereby provide an output signal based on the comparison. The switching circuit may be configured to electrically couple the virtual voltage rail to the voltage supply node depending upon the output signal. In some embodiments, the switching circuit may be implemented using either a PMOS transistor or an NMOS transistor, although other embodiments may employ other switching circuits.

Abstract translation: 公开了包括耦合到虚拟电压轨的多个存储单元的存储器电路。 多个存储单元可以形成例如SRAM阵列的子阵列。 开关电路可以耦合在虚拟电压轨和电压供应节点之间，并且比较器可以被耦合以将存在于虚拟电压轨上的电压电平与参考电压进行比较，从而基于该比较来提供输出信号。 开关电路可以被配置为根据输出信号将虚拟电压轨电耦合到电压供应节点。 在一些实施例中，可以使用PMOS晶体管或NMOS晶体管来实现开关电路，尽管其他实施例可以采用其他开关电路。

公开(公告)号：EP3309674A1

公开(公告)日：2018-04-18

申请号：EP17205934.7

申请日：2014-04-03

Applicant: Apple Inc.

Inventor： BISWAS, Sukalpa ,  SHIU, Shinye ,  DE LA CROPTE DE CHANTERAC, Cyril ,  GULATI, Manu ,  DESAI, Pulkit ,  HU, Rong Zhang

IPC: G06F3/14 ,  G09G5/393 ,  G09G5/395 ,  G09G5/00

CPC classification number: G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract translation: 在一个实施例中，一种系统包括：存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示器控制器。 系统可以被配置为检测正被显示的图像基本上是静态的，并且可以被配置为使得显示控制器向存储器高速缓存中请求分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时候，帧缓冲器数据可能不会被缓存在存储器缓存中，并且电源管理配置可以允许关闭/减小存储器缓存中的尺寸。