公开(公告)号：WO2020041649A1

公开(公告)日：2020-02-27

申请号：PCT/US2019/047807

申请日：2019-08-23

Applicant: APPLE INC.

Inventor： KEIL, Shane, J. ,  MATHEWS, Gregory, S. ,  NUKALA, Lakshmi Narasimha Murthy ,  MAGUDILU VIJAYARAJ, Thejasvi ,  HSIUNG, Kai Lun ,  LIU, Yanzhe ,  BISWAS, Sukalpa

IPC: G06F13/16

Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

公开(公告)号：WO2013036477A1

公开(公告)日：2013-03-14

申请号：PCT/US2012/053656

申请日：2012-09-04

Applicant: APPLE INC. ,  CHEN, Hao ,  NOTANI, Rakesh L. ,  BISWAS, Sukalpa

Inventor： CHEN, Hao ,  NOTANI, Rakesh L. ,  BISWAS, Sukalpa

IPC: G11C7/00

CPC classification number: G06F13/1689

Abstract: Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is configured to determine the adjusted time value by using the initial time value to sample the data strobe signal.

Abstract translation: 公开了关于确定何时数据选通信号对于捕获数据有效的技术。 在一个实施例中，公开了一种装置，其包括存储器接口电路，其被配置为基于数据选通信号来确定用于从存储器捕获数据的初始时间值。 在一些实施例中，存储器接口电路可以通过从存储器读取已知值来确定该初始时间值。 在一个实施例中，存储器接口电路还被配置为确定用于捕获数据的经调整的时间值，其中存储器接口电路被配置为通过使用初始时间值来对数据选通信号进行采样来确定调整的时间值。

公开(公告)号：WO2012036905A1

公开(公告)日：2012-03-22

申请号：PCT/US2011/049940

申请日：2011-08-31

Applicant: APPLE INC. ,  BISWAS, Sukalpa ,  CHEN, Hao ,  WADHAWAN, Ruchi

Inventor： BISWAS, Sukalpa ,  CHEN, Hao ,  WADHAWAN, Ruchi

IPC: G06F13/00

CPC classification number: G06F13/1642 ,  G06F13/1626

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

Abstract translation: 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数在不同端口上接收的调度操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

公开(公告)号：WO2014172078A1

公开(公告)日：2014-10-23

申请号：PCT/US2014/031699

申请日：2014-03-25

Applicant: APPLE INC.

Inventor： BISWAS, Sukalpa ,  KLINGAUF, Wolfgang H. ,  HU, Rong Zhang ,  SHIU, Shinye

IPC: G06F12/08 ,  G09G5/395 ,  G06F1/32

CPC classification number: G06F12/0871 ,  G06F1/3218 ,  G06F1/3275 ,  G06F12/0864 ,  G06F12/0893 ,  G06F12/122 ,  G06F2212/1028 ,  G06F2212/171 ,  G06F2212/6046 ,  G09G5/395 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2360/121 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods and systems for cache allocation schemes optimized for browsing applications. A memory controller includes a memory cache for reducing the number of requests that access off-chip memory. When an idle screen use case is detected, the frame buffer is allocated to the memory cache using a sequential allocation mode. Pixels are allocated to indexes of a given way in a sequential fashion, and then each way is accessed in a sequential fashion. When a given way is being accessed, the other ways of the memory cache are put into retention mode to reduce the leakage power.

Abstract translation: 针对浏览应用程序优化的缓存分配方案的方法和系统。 存储器控制器包括用于减少访问片外存储器的请求数量的存储器高速缓存。 当检测到空闲屏幕用例时，使用顺序分配模式将帧缓冲区分配给存储器高速缓存。 以顺序方式将像素分配给给定方式的索引，然后以顺序的方式访问各种方式。 当访问给定的方式时，存储器高速缓存的其他方式进入保留模式以减少泄漏功率。

公开(公告)号：WO2014052589A2

公开(公告)日：2014-04-03

申请号：PCT/US2013/061919

申请日：2013-09-26

Applicant: APPLE INC.

Inventor： BISWAS, Sukalpa ,  SHIU, Shinye ,  WANG, James ,  HU, Robert

IPC: G06F12/08

CPC classification number: G06F12/126 ,  G06F1/3225 ,  G06F12/0842

Abstract: Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID.

Abstract translation: 用于释放一个或多个组ID的高速缓存行粘性状态的方法和设备。 粘性删除引擎遍历系统缓存的标签内存，寻找与第一组ID相匹配的第一组ID，该ID将从系统缓存中清除其缓存行。 引擎清除属于第一组ID的每个缓存行的粘滞状态。 如果引擎收到第二组ID的释放请求，则引擎会记录当前索引以通过标签内存记录其进度。 然后，引擎继续浏览标签内存，查找与第一组或第二组ID相匹配的内容。 引擎回卷到标签内存的开始位置，继续走路，直到达到第二组ID的已记录索引。

公开(公告)号：EP2901287A2

公开(公告)日：2015-08-05

申请号：EP13774572.5

申请日：2013-09-26

Applicant: Apple Inc.

Inventor： BISWAS, Sukalpa ,  SHIU, Shinye ,  WANG, James ,  HU, Robert

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/126 ,  G06F1/3225 ,  G06F12/0842

Abstract: Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID.

Abstract translation: 用于释放用于一个或多个组ID的高速缓存行的粘性状态的方法和装置。 粘性移除引擎遍历系统缓存的标签存储器，寻找与从系统高速缓存清除其高速缓存行的第一组ID的匹配。 引擎清除属于第一组ID的每条缓存线的粘性状态。 如果引擎接收到第二组ID的释放请求，则引擎记录当前索引以通过标记存储器记录其进度。 然后，引擎继续穿过标签内存，寻找与第一或第二组ID的匹配。 发动机绕包到标签存储器的开头，并继续其行进直到到达第二组ID的记录索引。

公开(公告)号：EP3449482A1

公开(公告)日：2019-03-06

申请号：EP17820683.5

申请日：2017-03-06

Applicant: Apple Inc.

Inventor： BISWAS, Sukalpa ,  NEMATI, Farid

IPC: G11C5/04 ,  G11C5/06

公开(公告)号：EP3852107A1

公开(公告)日：2021-07-21

申请号：EP21162067.9

申请日：2017-03-06

Applicant: Apple Inc.

Inventor： BISWAS, Sukalpa ,  NEMATI, Farid

IPC: G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4093 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type maybe a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type maybe on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

公开(公告)号：WO2018052712A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/049290

申请日：2017-08-30

Applicant: APPLE INC.

Inventor： JETER, Robert E. ,  DENG, Liang ,  HSIUNG, Kai Lun ,  GULATI, Manu ,  NOTANI, Rakesh L. ,  BISWAS, Sukalpa ,  MALLADI, Venkata Ramana ,  MATHEWS, Gregory S. ,  ZHENG, Enming ,  FAURE, Fabien S.

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0634 ,  G06F1/08 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/1689 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

Abstract translation: 用于改善存储器控制器功率管理技术的系统，设备和方法。 一种设备包括控制逻辑，一个或多个存储器控制器和一个或多个存储器设备。 如果给定存储器控制器的通信量和/或队列深度的量下降到阈值以下，则提供给给定存储器控制器和相应存储器设备的时钟频率被降低。 在一个实施例中，时钟频率减半。 如果业务量和/或队列深度增加到阈值以上，则时钟频率增加回到其原始频率。 时钟频率可以通过将时钟分频器使用的除数加倍来调整，这可以在原始速率和降低的速率之间进行快速切换。 这反过来又允许在低功率状态和正常功率状态之间更频繁地切换，从而导致存储器控制器和存储器设备更高效地工作。

公开(公告)号：WO2014052383A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/061572

申请日：2013-09-25

Applicant: APPLE INC.

Inventor： BISWAS, Sukalpa ,  SHIU, Shinye ,  KELLER, James B.

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0859 ,  G06F12/126 ,  Y02D10/13

Abstract: Methods and apparatuses for utilizing a data pending state for cache misses in a system cache. To reduce the size of a miss queue that is searched by subsequent misses, a cache line storage location is allocated in the system cache for a miss and the state of the cache line storage location is set to data pending. A subsequent request that hits to the cache line storage location will detect the data pending state and as a result, the subsequent request will be sent to a replay buffer. When the fill for the original miss comes back from external memory, the state of the cache line storage location is updated to a clean state. Then, the request stored in the replay buffer is reactivated and allowed to complete its access to the cache line storage location.

Abstract translation: 用于在系统高速缓存中利用数据挂起状态用于高速缓存未命中的方法和装置。 为了减少由后续未命中搜索的未命中队列的大小，高速缓存行存储位置在系统高速缓存中被分配为未命中，并且高速缓存行存储位置的状态被设置为数据挂起。 命中缓存行存储位置的后续请求将检测数据待处理状态，结果将后续请求发送到重放缓冲区。 当原始错误的填充从外部存储器返回时，缓存行存储位置的状态被更新为干净状态。 然后，重新启动存储在重放缓冲区中的请求，并允许其完成对高速缓存行存储位置的访问。