公开(公告)号：WO2011006096A2

公开(公告)日：2011-01-13

申请号：PCT/US2010/041570

申请日：2010-07-09

Applicant: APPLE INC. ,  WANG, James ,  CHEN, Zongjian ,  KELLER, James B. ,  MILLET, Timothy J.

Inventor： WANG, James ,  CHEN, Zongjian ,  KELLER, James B. ,  MILLET, Timothy J.

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0223 ,  G06F12/08 ,  G06F2212/2515 ,  Y02D10/13

Abstract: In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

Abstract translation: 在一个实施例中，提供了一种非透明存储器单元，其包括非透明存储器和控制电路。 控制电路可以将非透明存储器作为一组非透明存储块来管理。 在一个或多个处理器上执行的软件可以请求处理数据的非透明存储器块。 控制电路可以分配第一块，并且可以返回分配块的地址（或其他指示），使得软件可以访问该块。 控制电路还可以提供非透明存储器与非透明存储器单元耦合到的主存储器系统之间的自动数据移动。 例如，自动数据移动可以包括将数据从主存储器系统填充到分配的块，或者在分配的块的处理完成之后将分配的块中的数据清除到主存储器系统。

公开(公告)号：WO2014052383A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/061572

申请日：2013-09-25

Applicant: APPLE INC.

Inventor： BISWAS, Sukalpa ,  SHIU, Shinye ,  KELLER, James B.

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0859 ,  G06F12/126 ,  Y02D10/13

Abstract: Methods and apparatuses for utilizing a data pending state for cache misses in a system cache. To reduce the size of a miss queue that is searched by subsequent misses, a cache line storage location is allocated in the system cache for a miss and the state of the cache line storage location is set to data pending. A subsequent request that hits to the cache line storage location will detect the data pending state and as a result, the subsequent request will be sent to a replay buffer. When the fill for the original miss comes back from external memory, the state of the cache line storage location is updated to a clean state. Then, the request stored in the replay buffer is reactivated and allowed to complete its access to the cache line storage location.

Abstract translation: 用于在系统高速缓存中利用数据挂起状态用于高速缓存未命中的方法和装置。 为了减少由后续未命中搜索的未命中队列的大小，高速缓存行存储位置在系统高速缓存中被分配为未命中，并且高速缓存行存储位置的状态被设置为数据挂起。 命中缓存行存储位置的后续请求将检测数据待处理状态，结果将后续请求发送到重放缓冲区。 当原始错误的填充从外部存储器返回时，缓存行存储位置的状态被更新为干净状态。 然后，重新启动存储在重放缓冲区中的请求，并允许其完成对高速缓存行存储位置的访问。

公开(公告)号：WO2014047239A1

公开(公告)日：2014-03-27

申请号：PCT/US2013/060528

申请日：2013-09-19

Applicant: APPLE INC.

Inventor： SAUND, Gurjeet S. ,  KELLER, James B. ,  GULATI, Manu ,  BISWAS, Sukalpa

IPC: G06F13/16

CPC classification number: G06F13/1605 ,  Y02D10/14

Abstract: In some embodiments, a system includes a shared, high bandwidth resource (e.g. a memory system), multiple agents configured to communicate with the shared resource, and a communication fabric coupling the multiple agents to the shared resource. The communication fabric may be equipped with limiters configured to limit bandwidth from the various agents based on one or more performance metrics measured with respect to the shared, high bandwidth resource. For example, the performance metrics may include one or more of latency, number of outstanding transactions, resource utilization, etc. The limiters may dynamically modify their limit configurations based on the performance metrics. In an embodiment, the system may include multiple thresholds for the performance metrics, and exceeding a given threshold may include modifying the limiters in the communication fabric. There may be hysteresis implemented in the system as well in some embodiments, to reduce the frequency of transitions between configurations.

Abstract translation: 在一些实施例中，系统包括共享的高带宽资源（例如，存储器系统），被配置为与共享资源通信的多个代理以及将多个代理耦合到共享资源的通信结构。 通信结构可以配备有限制器，其被配置为基于针对共享的高带宽资源测量的一个或多个性能度量来限制来自各种代理的带宽。 例如，性能度量可以包括延迟，未决事务数量，资源利用等中的一个或多个。限制器可以基于性能度量动态修改其限制配置。 在一个实施例中，系统可以包括用于性能度量的多个阈值，并且超过给定阈值可以包括修改通信结构中的限制器。 在一些实施例中，也可能在系统中实现滞后，以减少配置之间的转换频率。

公开(公告)号：EP2452265B1

公开(公告)日：2018-10-24

申请号：EP10732817.1

申请日：2010-07-09

Applicant: Apple Inc.

Inventor： WANG, James ,  CHEN, Zongjian ,  KELLER, James B. ,  MILLET, Timothy J.

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0223 ,  G06F12/08 ,  G06F2212/2515 ,  Y02D10/13

Abstract: In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

公开(公告)号：EP2452265A2

公开(公告)日：2012-05-16

申请号：EP10732817.1

申请日：2010-07-09

Applicant: Apple Inc.

Inventor： WANG, James ,  CHEN, Zongjian ,  KELLER, James B. ,  MILLET, Timothy J.

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0223 ,  G06F12/08 ,  G06F2212/2515 ,  Y02D10/13

Abstract: In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

Abstract translation: 在一个实施例中，提供了一种非透明存储器单元，其包括非透明存储器和控制电路。 控制电路可以将非透明存储器作为一组非透明存储器块来管理。 在一个或多个处理器上执行的软件可以请求处理数据的非透明存储器块。 控制电路可以分配第一块，并且可以返回所分配的块的地址（或其他指示），使得软件可以访问块。 控制电路还可以在非透明存储器与非透明存储器单元耦合到的主存储器系统之间提供自动数据移动。 例如，自动数据移动可以包括在分配的块的处理完成之后从主存储器系统填充数据到所分配的块，或者将分配的块中的数据刷新到主存储器系统。

公开(公告)号：EP1922629B1

公开(公告)日：2010-11-24

申请号：EP06801345.7

申请日：2006-08-11

Applicant: Apple Inc.

Inventor： SUBRAMANIAN, Sridhar P. ,  KELLER, James B. ,  YIU, George Kong ,  WADHAWAN, Ruchi ,  GUNNA, Ramesh

IPC: G06F13/40 ,  G06F13/362

CPC classification number: G06F13/362 ,  G06F13/4022

Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.