公开(公告)号：US20240194646A1

公开(公告)日：2024-06-13

申请号：US18374725

申请日：2023-09-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chen-Yu Wang ,  Chih-Hao Chiang ,  Pai-Sheng Cheng ,  Kung-An Lin ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Wen-Cheng Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/13541 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

公开(公告)号：US20230170301A1

公开(公告)日：2023-06-01

申请号：US17972648

申请日：2022-10-25

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Chun-Ting Kuo ,  Lung-Hua Ho ,  Chih-Ming Kuo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/552

CPC classification number: H01L23/5286 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/552

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a connection layer and wire layers. The dielectric layer is disposed on a surface of the substrate and includes vias showing the surface. The connection layer is disposed on the dielectric layer, a first connection portion of the connection layer is located in the vias and connected to the surface, a second connection portion of the connection layer is connected to the dielectric layer. A first ground portion of the ground metal layer is connected to the first connection portion of the connection layer, and a second ground portion of the ground metal layer is connected to the second connection portion of the connection layer. Each of the wire layers is disposed on the second connection portion of the connection layer, and the second ground portion is located between the adjacent wire layers.

公开(公告)号：US20230378044A1

公开(公告)日：2023-11-23

申请号：US18109337

申请日：2023-02-14

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Chih-Hao Chiang ,  Chen-Yu Wang ,  Kung-An Lin ,  Pai-Sheng Cheng

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13014 ,  H01L2224/16227

Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.