公开(公告)号：US20240194646A1

公开(公告)日：2024-06-13

申请号：US18374725

申请日：2023-09-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chen-Yu Wang ,  Chih-Hao Chiang ,  Pai-Sheng Cheng ,  Kung-An Lin ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Wen-Cheng Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/13541 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

公开(公告)号：US20230135424A1

公开(公告)日：2023-05-04

申请号：US17896171

申请日：2022-08-26

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shrane-Ning Jenq ,  Wen-Cheng Hsu ,  Chen-Yu Wang ,  Chih-Ming Kuo ,  Chwan-Tyaw Chen ,  Lung-Hua Ho

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/311 ,  H01L21/3213 ,  C23C18/54 ,  C23C28/02 ,  C25D7/12

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

公开(公告)号：US12224183B2

公开(公告)日：2025-02-11

申请号：US17896171

申请日：2022-08-26

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shrane-Ning Jenq ,  Wen-Cheng Hsu ,  Chen-Yu Wang ,  Chih-Ming Kuo ,  Chwan-Tyaw Chen ,  Lung-Hua Ho

IPC: H01L21/48 ,  C23C18/54 ,  C23C28/02 ,  C25D7/12 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/498 ,  H01L23/00

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.