公开(公告)号：DE2233597A1

公开(公告)日：1973-01-18

申请号：DE2233597

申请日：1972-07-07

Applicant: CIT ALCATEL

Inventor： STENSTROM CLAUDE ,  LAMBOURG MICHEL ,  DUPREZ ROBERT

IPC: H04J3/07 ,  H04L1/10

Abstract: 1394561 Digital transmission; error correction COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT - ALCATEL 5 July 1972 [8 July 1971] 31537/72 Heading H4P Superfluous bits in a data bit train, called padding bits, are identified by further bits called padding indicators, and if the binary valves of the latter depart from a predetermined sequence, an error is implied which the system corrects by inverting the next padding indicator. A data bit train (lower line Fig. 1a, 1b 1c) is sampled at a higher frequency, upper line, so that a data bit is sometimes sampled twice (a, e). These are the padding bits, and are moved to the third bit position of each triplet of bits. The received train includes as every fourth bit (not seen in Fig. 1) the padding indicator bit. If this is 1, the preceding bit is a padding bit; if it is 0 the preceding bit is not a padding bit; it is data. These padding indicators occur with the pattern 01011, provided there is no transmission error and the frequencies of sample and data trains are within certain limits. Errors produce 3 1's or 2 0's in a row. A combination of two bi-stables (12, 13, Fig. 4, not shown) and logic NAND gates respond to the received train 5, out of which the padding indicators 1B are clocked at 11 by clock HB, to generate four possible patterns with the binary values of A B #A #B. Two 0's in the padding indicator sequence produce a transition of A=0, B=1 to A=0, B=0 which makes the circuit change the second 0 to a 1 in the corrected padding indicator signal IB 1 ; and three 1's produce a transition of A=1, B=1 to A=0, B = 0 which makes the circuit change the third 1 to a 0 in IB 1 . Apparent errors following and possibly arising from a correction are allowed to persist for a period of four received bits, and are only corrected then if they have not disappeared.