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    PROCEDE DE GENERATION D'UNE TOPOGRAPHIE D'UN CIRCUIT INTEGRE FDSOI
    1.
    发明专利
    PROCEDE DE GENERATION D'UNE TOPOGRAPHIE D'UN CIRCUIT INTEGRE FDSOI 未知

    公开(公告)号：FR2999746A1

    公开(公告)日：2014-06-20

    申请号：FR1261980

    申请日：2012-12-13

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

    Inventor： GIRAUD BASTIEN ,  FLATRESSE PHILIPPE ,  LE BOULAIRE MATTHIEU ,  NOEL JEAN-PHILIPPE

    IPC: G06F17/50 ,  H01L21/027 ,  H01L27/105

    Abstract: L'invention concerne un procédé de génération d'une topographie numérique de circuit intégré, comprenant les étapes de : -placement automatique des cellules standard dans au moins une rangée de la topographie, lesdites cellules comprenant au moins : -une première cellule comprenant un transistor nMOS (1n) ménagé à l'aplomb d'un caisson (11 2n) à dopage de type P, et comprenant un transistor pMOS (1p) ménagé à l'aplomb d'un caisson (112p) à dopage de type N, le caisson de type P et le caisson de type N étant disposés de part et d'autre d'un axe; et -une deuxième cellule incluant une diode, un caisson à dopage de type P et comportant un caisson à dopage de type N, la deuxième cellule comportant un élément de connexion métallique inférieur couplé à son caisson à dopage de type P.

    Method and device for characterizing a CMOS logic cell designed to be implemented in a technology of type partially depleted silicon-on-insulator (PD-SOI)
    2.
    发明专利
    Method and device for characterizing a CMOS logic cell designed to be implemented in a technology of type partially depleted silicon-on-insulator (PD-SOI) 未知

    公开(公告)号：FR2840454A1

    公开(公告)日：2003-12-05

    申请号：FR0206650

    申请日：2002-05-30

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： FLATRESSE PHILIPPE ,  CASU MARIO

    IPC: G06F17/50 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/58

    Abstract: The method comprises a modelling of the cell and a phase of determining the internal potentials (Vb) of transistors of the cell in a state of dynamic equilibrium, that is in steady state (AC), based on a functional simulation of the modelled cell by utilizing a binary stimulation signal (ST0) having an initial logic value, and on cancellation, within an error of precision, the sum of squares of variations of the quantities of charge in the floating substrates (B) of the transistors of the cell in the course of a period (P) including two successive transitions (TRn,TRn+1) of the stimulation signal. The phase of determining the internal potentials comprises, in an iterative manner and just to obtain the cancellation of the sum on one period of the stimulation signal, the functional simulation (MSIM) of the modelled cell delivering the variation of the quantities of charge in the floating substrates on the basis of the current values of the internal potentials, and an optimization treatment (MOPT) of the values of the internal potentials comprising the cancellation of an objective function equal to the sum. The method also comprises a phase of determining the potentials of the floating substrates in a state of static equilibrium (DC), and a phase of determining the difference between the speeds of evolution of the potentials of the floating substrates of the transistors with p-type channel and n-type channel of the cell between the state of static equilibrium and the state of dynamic equilibrium obtained for the stimulation signal. The internal potentials are determined after the first occurrence of the transition of the stimulation signal, and after the second occurrence of the transition of the stimulation signal; the internal potentials are determined according to the worst of the best case of the cell delay, on the basis of the internal potentials after each of the two occurrences, the internal potentials in the two states, and the difference of the evolution speeds. The cell comprises at least two complementary transistors connected to at least one input of the cell where the stimulation signal is applied. The cell comprises several pairs of complementary transistors connected to several inputs of the cell, and the stimulation signal is applied successively to each input delivered at output. The cell is decomposed into elementary cells, and the internal potentials are determined separately for each elementary cell in the state of dynamic equilibrium. The determination of the difference of the evolution speeds comprises the determination of the initial slope of a curve representing teh evolution. A device (claimed) implements the method (claimed).

    CIRCUIT INTEGRE COMPORTANT DES TRANSISTORS AVEC DES TENSIONS DE SEUIL DIFFERENTES
    3.
    发明专利
    CIRCUIT INTEGRE COMPORTANT DES TRANSISTORS AVEC DES TENSIONS DE SEUIL DIFFERENTES 未知

    公开(公告)号：FR2996956A1

    公开(公告)日：2014-04-18

    申请号：FR1259762

    申请日：2012-10-12

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

    Inventor： GIRAUD BASTIEN ,  FLATRESSE PHILIPPE ,  NOEL JEAN-PHILIPPE ,  PELLOUX FRAYER BERTRAND

    IPC: H01L27/088 ,  G11C11/412 ,  H03K17/04

    Abstract: Un circuit intégré (4) comporte des première et seconde cellules, comportant chacune des premier (10, 42) et second (12, 44) transistors FDSOI. Selon l'invention : -les première et seconde cellules sont accolées entre elles ; -des premier (20) et second (22) caissons de la première cellule et un premier caisson (50) de la seconde cellule présentent un dopage d'un premier type, un second caisson (52) de la seconde cellule présente un dopage opposé ; -le circuit comprend un dispositif de commande (5) pour appliquer une même polarisation électrique sur les caissons présentant le premier type de dopage ; -les transistors de la première cellule sont configurés pour présenter un premier niveau de tension de seuil, les transistors de la deuxième cellule sont configurés pour présenter un deuxième niveau de tension de seuil différent du premier niveau.

    CMOS logic cell characterizing method for accelerating simulation of temporal dependence of delays effect in design of CMOS logic cells
    4.
    发明专利
    CMOS logic cell characterizing method for accelerating simulation of temporal dependence of delays effect in design of CMOS logic cells 未知

    公开(公告)号：FR2845180A1

    公开(公告)日：2004-04-02

    申请号：FR0212022

    申请日：2002-09-27

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： POIROUX THIERRY ,  FLATRESSE PHILIPPE

    IPC: G06F17/50 ,  H01L21/8238

    Abstract: The method comprises the modelling of a CMOS logic cell and the phase of determining the internal potentials of the cell based on a functional simulation of the modelled cell by utilizing a simulation signal (ST) which is a periodic binary signal. The determining phase includes the injection of a charge into the floating substrate (B) of each transistor of the cell, where the charge is proportional to the variation of internal potential of the transistor determined in the course of a predetermined temporal interval (TC) of the simulation signal preceding the instant of injection and exempt of injection, in a manner to accelerate the charging or discharging of the floating substrate (B) of the transistor. The injection current corresponds to the injected charge so that after the injection the variation of internal potential (Vb) of the transistor attains a value n times the measured variation of internal potential. The value of n is determined on the basis of measuring the variation of internal potential in the course of a cycle of the simulation signal and an estimated amplitude of the variation of the internal potential of the transistor between its states of static equilibrium (DC) and dynamic equilibrium (AC, steady state). The value of a coefficient of proportionality (A) is determined on the basis of the measuring of the variation of the internal potential and the variation of charge of the transistor in the course of a cycle of the simulation signal and the duration of injection. The simulation signal (ST) comprises in each period a transition separating two levels, corresponding to 0 and 1, and the instant of injection is situated on a level and at a distance from the transition. The duration of current injection is greater than the temporal step of functional simulation and lesser than the duration of a level. The two instants of consecutive injection are separated by a duration equal to two periods of the simulation signal, or by one period in a variant of the method, and the temporal interval (TC) has a duration equal to a period of the simulation signal. The initial instant of the temporal interval precedes the instant of injection by 1.5 periods of the simulation signal, and the final instant precedes the injection instant by 0.5 period of the simulation signal, and the final instant precedes the instant of injection by 0.5 period fo the simulation signal. In the functional simulation each transistor is replaced by a model of the transistor associated with three modelled sources of voltage controlled by voltage, allowing to determine a target internal potential (Vbc) to be attained after injection, and a modelled current source delivering the injection current proportional to a difference between the target potential and the internal potential at the instant of inejction. The evolution of internal potentials of the transistors is determined from the state of static equilibrium to the state of dynamic equilibrium relative to rising and falling transitions of the simulation signal and for two initial values of the simulation signal, and the internal potentials corresponding to the best and worst cases of temporal delay are deduced. A device (claimed) for characterizing a CMOS logic cell implements the method (claimed) and comprises modelling means and processing means.

    10.
    发明专利
    未知

    公开(公告)号：FR2918518B1

    公开(公告)日：2009-09-25

    申请号：FR0704773

    申请日：2007-07-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： LHOSTIS NICOLAS ,  FLATRESSE PHILIPPE

    IPC: H03K17/00 ,  H03K17/16

    Abstract: A device monitors at least one power switch which is series-mounted with a logic core between a first and a second potential. A connection point between the switch and logic core is carried to a third potential. The switch is biased by a biasing potential. The device includes a feedback control module mounted between first and second potentials which is capable of generating a set potential representative of the third potential variation. A biasing module of the power switch is mounted between the first and second potentials, and generates a biasing potential based on the set potential. The biasing potential linearly varies with the decrease of the third potential.

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