公开(公告)号：FR2886761A1

公开(公告)日：2006-12-08

申请号：FR0505700

申请日：2005-06-06

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： MORAND YVES ,  POIROUX THIERRY ,  VINET MAUD

IPC: H01L21/8238

Abstract: Des électrodes de source (3) et de drain (4) sont constituées chacune par une alternance de premières (5) et secondes (6) couches en composé de germanium et silicium. Les premières couches (5) ont une concentration de germanium comprise entre 0% et 10% et les secondes couches (6) ont une concentration de germanium comprise entre 10% et 50%. Au moins un canal (1) relie deux secondes couches (6a, 6b) respectivement des électrodes de source (3) et de drain (4). Le procédé comporte la gravure de zones de source et de drain, reliées par une zone étroite, dans un empilement de couches (5, 6). Puis une oxydation thermique superficielle dudit empilement est effectuée de manière à oxyder le silicium du composé de germanium et silicium ayant une concentration de germanium comprise entre 10% et 50% et de manière à condenser le germanium Ge. Le silicium oxydé de la zone étroite est éliminé et un diélectrique (7) de grille et une grille (2) sont déposés sur le germanium condensé de la zone étroite.

公开(公告)号：FR2886763A1

公开(公告)日：2006-12-08

申请号：FR0505701

申请日：2005-06-06

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： MORAND YVES ,  POIROUX THIERRY ,  VINET MAUD

IPC: H01L29/161 ,  H01L21/20

Abstract: Le procédé comporte successivement la réalisation, sur un substrat (1), d'un empilement de couches (2, 3) comportant au moins une première couche (3) en composé de germanium et silicium ayant initialement une concentration de germanium comprise entre 10 et 50%. La première couche (3) est disposée entre des secondes couches (2) ayant des concentrations de germanium comprises entre 0 et 10%. Ensuite, on délimite par gravure, dans ledit empilement, une première zone (5) correspondant à l'élément à base de germanium et ayant au moins une première dimension latérale comprise entre 10nm et 500nm. Puis est effectuée une oxydation thermique, au moins latérale, de la première zone (5), de manière à ce qu'une couche de silice (6) se forme à la surface de la première zone (5) et en ce que, dans la première couche (3), une zone centrale (8) de germanium condensé se forme, constituant l'élément à base de germanium.

公开(公告)号：FR2845180A1

公开(公告)日：2004-04-02

申请号：FR0212022

申请日：2002-09-27

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： POIROUX THIERRY ,  FLATRESSE PHILIPPE

IPC: G06F17/50 ,  H01L21/8238

Abstract: The method comprises the modelling of a CMOS logic cell and the phase of determining the internal potentials of the cell based on a functional simulation of the modelled cell by utilizing a simulation signal (ST) which is a periodic binary signal. The determining phase includes the injection of a charge into the floating substrate (B) of each transistor of the cell, where the charge is proportional to the variation of internal potential of the transistor determined in the course of a predetermined temporal interval (TC) of the simulation signal preceding the instant of injection and exempt of injection, in a manner to accelerate the charging or discharging of the floating substrate (B) of the transistor. The injection current corresponds to the injected charge so that after the injection the variation of internal potential (Vb) of the transistor attains a value n times the measured variation of internal potential. The value of n is determined on the basis of measuring the variation of internal potential in the course of a cycle of the simulation signal and an estimated amplitude of the variation of the internal potential of the transistor between its states of static equilibrium (DC) and dynamic equilibrium (AC, steady state). The value of a coefficient of proportionality (A) is determined on the basis of the measuring of the variation of the internal potential and the variation of charge of the transistor in the course of a cycle of the simulation signal and the duration of injection. The simulation signal (ST) comprises in each period a transition separating two levels, corresponding to 0 and 1, and the instant of injection is situated on a level and at a distance from the transition. The duration of current injection is greater than the temporal step of functional simulation and lesser than the duration of a level. The two instants of consecutive injection are separated by a duration equal to two periods of the simulation signal, or by one period in a variant of the method, and the temporal interval (TC) has a duration equal to a period of the simulation signal. The initial instant of the temporal interval precedes the instant of injection by 1.5 periods of the simulation signal, and the final instant precedes the injection instant by 0.5 period of the simulation signal, and the final instant precedes the instant of injection by 0.5 period fo the simulation signal. In the functional simulation each transistor is replaced by a model of the transistor associated with three modelled sources of voltage controlled by voltage, allowing to determine a target internal potential (Vbc) to be attained after injection, and a modelled current source delivering the injection current proportional to a difference between the target potential and the internal potential at the instant of inejction. The evolution of internal potentials of the transistors is determined from the state of static equilibrium to the state of dynamic equilibrium relative to rising and falling transitions of the simulation signal and for two initial values of the simulation signal, and the internal potentials corresponding to the best and worst cases of temporal delay are deduced. A device (claimed) for characterizing a CMOS logic cell implements the method (claimed) and comprises modelling means and processing means.

公开(公告)号：FR3057104A1

公开(公告)日：2018-04-06

申请号：FR1659574

申请日：2016-10-04

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2 SAS

Inventor： BARRAL VINCENT ,  PLANES NICOLAS ,  CROS ANTOINE ,  HAENDLER SEBASTIEN ,  POIROUX THIERRY ,  WEBER OLIVIER ,  SCHEER PATRICK

IPC: H01L25/03 ,  H01L29/772

Abstract: L'invention concerne une puce électronique comprenant des transistors (TA, TB) à effet de champ de type FDSOI dont les régions de canal (44) sont dopées à un niveau moyen compris entre 1016 et 5* 1017 atomes/cm3 d'un type de conductivité opposé à celui des régions de drain (50A, 50B) et de source (48)

公开(公告)号：FR2886761B1

公开(公告)日：2008-05-02

申请号：FR0505700

申请日：2005-06-06

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： MORAND YVES ,  POIROUX THIERRY ,  VINET MAUD

IPC: H01L21/8238

Abstract: Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.

公开(公告)号：FR2886763B1

公开(公告)日：2007-08-03

申请号：FR0505701

申请日：2005-06-06

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： MORAND YVES ,  POIROUX THIERRY ,  VINET MAUD

Abstract: The method involves forming a stack by laminating an inner germanium silicon layer (3) between outer germanium silicon layers (2), in which the germanium concentration of the inner and outer germanium silicon layers are between 10 to 50 percent and between 0 to 10 percent, respectively. A silica layer (6) is formed on the surface of a main zone (5) by performing delineation and lateral thermal oxidation in the stack. Delineation process includes performing anisotropic plasma etching in the stack after deposition and photolithography of a photoresist. An independent claim is also included for: a germanium-based microelectronic component.

公开(公告)号：FR2845180B1

公开(公告)日：2004-12-17

申请号：FR0212022

申请日：2002-09-27

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： POIROUX THIERRY ,  FLATRESSE PHILIPPE

IPC: G06F17/50 ,  H01L21/8238

公开(公告)号：WO2008155379A3

公开(公告)日：2009-04-09

申请号：PCT/EP2008057773

申请日：2008-06-19

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  MAYER FREDERIC ,  CLAVELIER LAURENT ,  POIROUX THIERRY ,  BILLIOT GERARD

Inventor： MAYER FREDERIC ,  CLAVELIER LAURENT ,  POIROUX THIERRY ,  BILLIOT GERARD

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7855 ,  H01L29/41791 ,  H01L29/66795

Abstract: Field effect transistor (100) comprising: - a support layer (104), - a plurality of semiconductor based active zones (106), each active zone being intended to form a channel and disposed between two gates (112) situated one beside the other consecutively, the active zones and the gates being disposed on the support layer, each gate comprising a first face on the side of the support layer and a second face opposite the first face, - the second face of a first of the two gates being connected electrically to a first electrical contact (118, 122, 124) made on the second face of said first of the two gates, and the first face of a second of the two gates being connected electrically to a second electrical contact (118, 130, 132) passing through the support layer, the gates of the transistor not being electrically interconnected.

Abstract translation: 场效应晶体管（100）包括： - 支撑层（104）， - 多个基于半导体的有源区（106），每个有源区旨在形成通道并设置在位于另一个旁边的两个栅极（112）之间 连续地，活动区域和门设置在支撑层上，每个门包括在支撑层侧面的第一面和与第一面相对的第二面， - 两个门中的第一个的第二面被连接 电连接到在所述两个栅极中的所述第一栅极的第二面上形成的第一电触点（118,122,124），并且所述两个栅极中的第二栅极的第一面电连接到第二电触头（118,130,124） 132）通过支撑层，晶体管的栅极不是电互连的。

公开(公告)号：AT533184T

公开(公告)日：2011-11-15

申请号：AT07858219

申请日：2007-12-28

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： VINET MAUD ,  THOMAS OLIVIER ,  ROZEAU OLIVIER ,  POIROUX THIERRY

IPC: H01L27/11 ,  H01L21/8244

Abstract: The method involves forming structures (150) on a substrate (100), where the structure includes primary semiconductor blocks (110a) forming a primary grid from a double grid of a fin FET transistor, and secondary semiconductor blocks (120a) forming a secondary grid from the double grid of the transistors. The blocks are situated at two sides of a semi-conductor zone (115a), and are separated from the semiconductor zone by two dielectric zones (109a, 119a) of the grids. The semiconductor zone of the secondary block is doped using selective implantation of the primary block of the structure. An independent claim is also included for a microelectronic device e.g. static RAM cell, comprising a finest transistor.

公开(公告)号：AT515792T

公开(公告)日：2011-07-15

申请号：AT09159902

申请日：2009-05-11

Applicant: COMMISSARIAT ENERGIE ATOMIQUE

Inventor： VINET MAUD ,  POIROUX THIERRY ,  PREVITALI BERNARD

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

Abstract: The method involves depositing a metallic layer (132) covering lateral flanks of a channel on walls of holes, and siliconizing the flanks. Another metallic layer forming a source and a drain of a MOS transistor (100) with the siliconized portion of the flanks is deposited on the layer (132). The latter layer is mechano-chemically planarized with stop on a hard mask (118). A titanium, titanium nitride or tungsten based layer is deposited on the layer (132) after deposition of the layer (132). An oxide layer is deposited on the latter layer after deposition of the latter layer.