公开(公告)号：AT148242T

公开(公告)日：1997-02-15

申请号：AT93924899

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER E ,  MORIARTY MICHAEL ,  TAYLOR MARK

IPC: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：AU5440894A

公开(公告)日：1994-04-26

申请号：AU5440894

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER E ,  MORIARTY MICHAEL ,  TAYLOR MARK

IPC: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：CA2145884A1

公开(公告)日：1994-04-14

申请号：CA2145884

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： TAYLOR MARK ,  CULLEY PAUL R ,  MELO MARIA L ,  TIPLEY ROGER E

IPC: G06F13/364 ,  G06F15/163

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：AT170642T

公开(公告)日：1998-09-15

申请号：AT91305422

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER E

IPC: G06F12/08

Abstract: A method for achieving multilevel inclusion in a computer system with first and second level caches. The caches align themselves on a "way" basis by their respective cache controllers communicating with each other as to which blocks of data they are replacing and which of their cache ways are being filled with data. On first and second level cache read misses the first level cache controller provides way information to the second level cache controller to allow received data to be placed in the same way. On first level cache read misses and second level cache read hits, the second level cache controller provides way information the first level cache controller, which ignores its replacement indication and places data in the indicated way. On processor writes the first level cache controller caches the writes and provides the way information to the second level cache controller which also caches the writes and uses the way information to select the proper way for data storage. An inclusion bit is set on data in the second level cache that is duplicated in the first level cache. Multilevel inclusion allows the second level cache controller to perform the principal snooping responsibilities for both caches, thereby enabling the first level cache controller to avoid snooping duties until a first level cache snoop hit occurs. On a second level cache snoop hit, the second level cache controller checks the respective inclusion bit to determine if a copy of this data also resides in the first level cache. The first level cache controller is directed to snoop the bus only if the respective inclusion bit is set.

公开(公告)号：AU5297993A

公开(公告)日：1994-04-26

申请号：AU5297993

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  WOLFORD JEFF W ,  FRY WALTER G ,  TIPLEY ROGER E

IPC: G06F11/16 ,  G06F11/20

Abstract: A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

公开(公告)号：CA2044689A1

公开(公告)日：1991-12-16

申请号：CA2044689

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER E

IPC: G06F12/08 ,  G06F12/00

Abstract: MULTILEVEL INCLUSION IN MULTILEVEL CACHE HIERARCHIES A method for achieving multilevel inclusion in a computer system with first and second level caches. The caches align themselves on a "way" basis by their respective cache controllers communicating with each other as to which blocks of data they are replacing and which of their cache ways are being filled with data. On first and second level cache read misses the first level cache controller provides way information to the second level cache controller to allow received data to be placed in the same way. On first level cache read misses and second level cache read hits, the second level cache controller provides way information the first level cache controller, which ignores its replacement indication and places data in the indicated way. On processor writes the first level cache controller caches the writes and provides the way information to the second level cache controller which also caches the writes and uses the way information to select the proper way for data storage. An inclusion bit is set on data in the second level cache that is duplicated in the first level cache. Multilevel inclusion allows the second level cache controller to perform the principal snooping responsibilities for both caches, thereby enabling the first level cache controller to avoid snooping duties until a first level cache snoop hit occurs. On a second level cache snoop hit, the second level cache controller checks the respective inclusion bit to determine if a copy of this data also resides in the first level cache. The first level cache controller is directed to snoop the bus only if the respective inclusion bit is set.

公开(公告)号：DE69127773D1

公开(公告)日：1997-11-06

申请号：DE69127773

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： COLLINS MICHAEL J ,  TIPLEY ROGER E

IPC: G06F12/08 ,  G06F12/12

Abstract: An apparatus for performing LRU techniques for a 4 way set associative cache system. A RAM stores the ways representing the least recently used (LRU), most recently used (MRU) and LRU+1. The MRU-1 is developed by XORing the other three LRU way information values. Processor or snoop operation is determined and the way use aging information valued is based on snooping or processor operations. For processor operations the accessed or to be accessed way is set as the MRU, while in snoop operations, the way being accessed is set as the LRU. The aging of the remaining ways is shuffled accordingly. This shuffling occurs each cycle but is only stored on processor cache hit, processor read cache miss and snoop hit operations.

公开(公告)号：AU5441594A

公开(公告)日：1994-04-26

申请号：AU5441594

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： TAYLOR MARK ,  CULLEY PAUL R ,  MELO MARIA L ,  TIPLEY ROGER E

IPC: G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：CA2044488A1

公开(公告)日：1991-12-16

申请号：CA2044488

申请日：1991-06-13

Applicant: COMPAQ COMPUTER CORP

Inventor： COLLINS MICHAEL J ,  TIPLEY ROGER E

IPC: G06F12/02

Abstract: TRUE LEAST RECENTLY USED REPLACEMENT METHOD AND APPARATUS An apparatus for performing LRU techniques for a 4 way set associative cache system. A RAM stores the ways representing the least recently used (LRU), most recently used (MRU) and LRU+1. The MRU-1 is developed by XORing the other three LRU way information values. Processor or snoop operation is determined and the way use aging information valued is based on snooping or processor operations. For processor operations the accessed or to be accessed way is set as the MRU, while in snoop operations, the way being accessed is set as the LRU. The aging of the remaining ways is shuffled accordingly. This shuffling occurs each cycle but is only stored on processor cache hit, processor read cache miss and snoop hit operations.

公开(公告)号：DE69130086T2

公开(公告)日：1999-01-21

申请号：DE69130086

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER E

IPC: G06F12/08

Abstract: A method for achieving multilevel inclusion in a computer system with first and second level caches. The caches align themselves on a "way" basis by their respective cache controllers communicating with each other as to which blocks of data they are replacing and which of their cache ways are being filled with data. On first and second level cache read misses the first level cache controller provides way information to the second level cache controller to allow received data to be placed in the same way. On first level cache read misses and second level cache read hits, the second level cache controller provides way information the first level cache controller, which ignores its replacement indication and places data in the indicated way. On processor writes the first level cache controller caches the writes and provides the way information to the second level cache controller which also caches the writes and uses the way information to select the proper way for data storage. An inclusion bit is set on data in the second level cache that is duplicated in the first level cache. Multilevel inclusion allows the second level cache controller to perform the principal snooping responsibilities for both caches, thereby enabling the first level cache controller to avoid snooping duties until a first level cache snoop hit occurs. On a second level cache snoop hit, the second level cache controller checks the respective inclusion bit to determine if a copy of this data also resides in the first level cache. The first level cache controller is directed to snoop the bus only if the respective inclusion bit is set.