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公开(公告)号：AU5297993A
公开(公告)日：1994-04-26
申请号：AU5297993
申请日：1993-09-30
Applicant: COMPAQ COMPUTER CORP
Inventor： LANDRY JOHN A , WOLFORD JEFF W , FRY WALTER G , TIPLEY ROGER E
Abstract: A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.
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Patent Agency Ranking
公开(公告)号：JPH11316738A
公开(公告)日：1999-11-16
申请号：JP36545998
申请日：1998-12-22
Applicant: COMPAQ COMPUTER CORP
Inventor： ELLIOTT ROBERT C , MELO MARIA L , ALZIEN KHALDOUN , FOSTER JOSEPH E , FRY WALTER G
Abstract: PROBLEM TO BE SOLVED: To provide a just mediation mechanism to an isochronous device. SOLUTION: A bus interface device controlling access to a processor bus 103 and a peripheral bus 114 from a memory is provided with a CPU interface 204 receiving a memory request from a micro processor, a peripheral bus interface 212 receiving the memory request from the peripheral bus, a memory controller 210 controlling access to the memory and a queue manager 206. The manager 206 mediates pending requests in the respective interfaces by using the round robin mediation algorithm. Thus, just mediation is realized.
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公开(公告)号：AU5403394A
公开(公告)日：1994-04-26
申请号：AU5403394
申请日：1993-09-30
Applicant: COMPAQ COMPUTER CORP
Inventor： WOLFORD JEFF W , FRY WALTER G
IPC: G06F12/08
Abstract: A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.
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公开(公告)号：CA2148186A1
公开(公告)日：1995-11-05
申请号：CA2148186
申请日：1995-04-28
Applicant: COMPAQ COMPUTER CORP
Inventor： JACKSON MICHAEL T , FRY WALTER G , GOODRUM ALAN L
IPC: G06F12/08 , G06F12/0811 , G06F12/0831 , G06F13/14
Abstract: A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system and a third level external cache system. The second level cache system is a conventional, high speed, SRAM-based, writeback cache system. The third level cache system is a large, writethrough cache system developed using conventional DRAMs as used in the main memory subsystem of the computer system. The three cache systems are arranged between the CPU and the host bus in a serial fashion. Because of the large size of the third level cache, a high hit rate is developed so that operations are not executed on the host bus but are completed locally on the processor board, reducing the use of the host bus by an individual processor board. This allows additional processor boards to be installed in the computer system without saturating the host bus. The third level cache system is organized as a writethrough cache. However, the shared or exclusive status of any cached data is also stored. If the second level cache performs a write allocate cycle and the data is exclusive in the third level cache, the data is provided directly from the third level cache, without requiring an access to main memory, reducing the use of the host bus.
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公开(公告)号：CA2145885A1
公开(公告)日：1994-04-14
申请号：CA2145885
申请日：1993-09-30
Applicant: COMPAQ COMPUTER CORP
Inventor： FRY WALTER G , WOLFORD JEFF W
Abstract: A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.
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公开(公告)号：AU5297893A
公开(公告)日：1994-04-26
申请号：AU5297893
申请日：1993-09-30
Applicant: COMPAQ COMPUTER CORP
Inventor： FRY WALTER G , WOLFORD JEFF W
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