公开(公告)号：DE69626485T2

公开(公告)日：2003-09-11

申请号：DE69626485

申请日：1996-12-10

Applicant: COMPAQ COMPUTER CORP

Inventor： WANNER CHRISTOPHER C ,  STEVENS JEFFREY C ,  LESTER ROBERT A ,  RILEY DWIGHT D ,  MAGUIRE DAVID J ,  EDWARDS JAMES R

IPC: G06F13/12 ,  G06F13/28

公开(公告)号：DE69626485D1

公开(公告)日：2003-04-10

申请号：DE69626485

申请日：1996-12-10

Applicant: COMPAQ COMPUTER CORP

Inventor： WANNER CHRISTOPHER C ,  STEVENS JEFFREY C ,  LESTER ROBERT A ,  RILEY DWIGHT D ,  MAGUIRE DAVID J ,  EDWARDS JAMES R

IPC: G06F13/12 ,  G06F13/28

公开(公告)号：DE69626231T2

公开(公告)日：2003-07-17

申请号：DE69626231

申请日：1996-02-26

Applicant: COMPAQ COMPUTER CORP

Inventor： LESTER ROBERT A ,  WOLFORD JEFF W

IPC: G06F13/36 ,  G06F13/40

Abstract: An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.

公开(公告)号：DE69626231D1

公开(公告)日：2003-03-27

申请号：DE69626231

申请日：1996-02-26

Applicant: COMPAQ COMPUTER CORP

Inventor： LESTER ROBERT A ,  WOLFORD JEFF W

IPC: G06F13/36 ,  G06F13/40

Abstract: An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.

公开(公告)号：DE69634182T2

公开(公告)日：2005-06-30

申请号：DE69634182

申请日：1996-02-27

Applicant: COMPAQ COMPUTER CORP

Inventor： WOLFORD JEFF W ,  LESTER ROBERT A

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/362

Abstract: An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.

公开(公告)号：DE69634182D1

公开(公告)日：2005-02-24

申请号：DE69634182

申请日：1996-02-27

Applicant: COMPAQ COMPUTER CORP

Inventor： WOLFORD JEFF W ,  LESTER ROBERT A

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/362

Abstract: An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.