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    FULL ADDRESS AND ODD BOUNDARY DIRECT MEMORY ACCESS CONTROLLER
    1.
    发明专利
    FULL ADDRESS AND ODD BOUNDARY DIRECT MEMORY ACCESS CONTROLLER 未知

    公开(公告)号：CA2007443A1

    公开(公告)日：1990-08-07

    申请号：CA2007443

    申请日：1990-01-09

    Applicant: COMPAQ COMPUTER CORP

    Inventor： WANNER CHRISTOPHER C ,  GOODRUM ALAN L ,  CULLEY PAUL R

    IPC: G06F12/08 ,  G06F13/28 ,  G06F12/02

    Abstract: FULL ADDRESS AND ODD BOUNDARY DIRECT MEMORY ACCESS CONTROLLER The computer system disclosed includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DNA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.

    Arrangement of dma, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system
    2.
    发明专利
    Arrangement of dma, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system 未知

    公开(公告)号：AU5297093A

    公开(公告)日：1994-04-26

    申请号：AU5297093

    申请日：1993-09-29

    Applicant: COMPAQ COMPUTER CORP

    Inventor： CULLEY PAUL R ,  LANDRY JOHN A ,  MAYER DALE J ,  WANNER CHRISTOPHER C ,  MCSWAIN GUY E

    IPC: G06F13/24 ,  G06F13/32 ,  G06F15/80

    Abstract: An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

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