公开(公告)号：EP0924621A3

公开(公告)日：2000-06-28

申请号：EP98310482.9

申请日：1998-12-18

Applicant: Compaq Computer Corporation

Inventor： Elliott, Robert C. ,  Alzien, Khaldoun ,  Melo, Maria L. ,  Foster, Joseph E. ,  Fry, Walter G.

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1642 ,  G06F13/4031

Abstract: A computer system includes a bridge logic unit for interfacing between a microprocessor coupled to a processor bus, a first peripheral device coupled to a first peripheral bus such as a PCI bus, and a main memory coupled to a memory bus. Additional peripheral buses may further be connected to the bridge logic unit. The bridge logic unit includes a respective interface for each bus from which a memory request may be initiated. For example, the bridge logic unit may include a CPU interface configured to receive memory requests from the microprocessor, and a PCI interface configured to receive memory requests from a PCI bus peripheral. and an AGP interface configured to receive memory requests from an AGP/PCI bus peripheral. Additional interfaces are provided for any further buses supported by the system. A memory queue manager is coupled to receive memory requests from each of the interfaces and to provide the requests to a memory controller independent of the source of the request. In one embodiment, the memory queue manager includes a read request queue for receiving memory read requests, and a write request queue for receiving memory write requests. A queue arbiter is provided to arbitrate among requests from the various interfaces to determine a particular request which should be loaded within one of the queues (i.e., either the read request queue or the write request queue) of the memory queue manager. The queue arbiter is configured to take only a single request at a time from each interface. and implements a round-robin arbitration algorithm.

公开(公告)号：EP0924621A2

公开(公告)日：1999-06-23

申请号：EP98310482.9

申请日：1998-12-18

Applicant: Compaq Computer Corporation

Inventor： Elliott, Robert C. ,  Alzien, Khaldoun ,  Melo, Maria L. ,  Foster, Joseph E. ,  Fry, Walter G.

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1642 ,  G06F13/4031

Abstract: A computer system includes a bridge logic unit for interfacing between a microprocessor coupled to a processor bus, a first peripheral device coupled to a first peripheral bus such as a PCI bus, and a main memory coupled to a memory bus. Additional peripheral buses may further be connected to the bridge logic unit. The bridge logic unit includes a respective interface for each bus from which a memory request may be initiated. For example, the bridge logic unit may include a CPU interface configured to receive memory requests from the microprocessor, and a PCI interface configured to receive memory requests from a PCI bus peripheral. and an AGP interface configured to receive memory requests from an AGP/PCI bus peripheral. Additional interfaces are provided for any further buses supported by the system. A memory queue manager is coupled to receive memory requests from each of the interfaces and to provide the requests to a memory controller independent of the source of the request. In one embodiment, the memory queue manager includes a read request queue for receiving memory read requests, and a write request queue for receiving memory write requests. A queue arbiter is provided to arbitrate among requests from the various interfaces to determine a particular request which should be loaded within one of the queues (i.e., either the read request queue or the write request queue) of the memory queue manager. The queue arbiter is configured to take only a single request at a time from each interface. and implements a round-robin arbitration algorithm.

Abstract translation: 一种计算机系统，包括：用于耦合到一个处理器总线，耦合到第一外围总线的第一外围设备的微处理器之间的接口桥接逻辑单元：例如PCI总线，以及耦合到存储器总线的主存储器。 附加的外围总线可连接另外的桥接逻辑单元。 桥接逻辑单元包括用于从该存储器请求可被启动的每个总线一个respectivement接口。 对于实施例，桥接逻辑单元可以包括被配置为从所述微处理器接收的存储器请求CPU接口，并且被配置为接收来自PCI总线外围设备的存储器请求PCI接口。 和在AGP接口被配置为从在AGP / PCI总线外围设备接收存储器请求。 提供了额外的接口，用于由系统支持的任何进一步的总线。存储器队列管理器被耦合以接收来自每个接口的存储器请求，并提供请求到存储控制器独立于请求的来源的。 在一个中，实施例存储器队列管理器包括：用于接收存储器读取请求的读取请求队列，以及用于接收存储器写请求的写requestQueueLimit。 本发明提供一种仲裁器队列从各种接口请求之间进行仲裁，以确定地挖掘应的存储器队列管理器的队列（即，无论是读requestQueueLimit或写请求队列）中的一个内被加载特定的请求。 队列仲裁器被配置为采取只在来自各界面的时间的单个请求。 并实现了循环仲裁算法。

公开(公告)号：EP0902356A2

公开(公告)日：1999-03-17

申请号：EP98307111.9

申请日：1998-09-03

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Elliott, Robert C.

IPC: G06F3/14

CPC classification number: G09G5/39 ,  G06F3/14 ,  G06F12/1027 ,  G06F12/1081 ,  G09G5/363 ,  G09G2360/121 ,  G09G2360/125

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in the computer system physical memory, and feature flags that may be used to customize the associated page of graphics data. One of the feature flags is used as a link bit for each GART table entry such that when the core logic chipset reads selected ones of the GART table entries stored in the system memory, it stores a first one of the selected ones in its cache memory and determines if the link bit thereof is set. If the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in the cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in the cache memory until one of the link bits thereof is determined not to be set.

Abstract translation: 具有作为加速图形端口（“AGP”）总线设备（诸如图形控制器）和主机处理器之间的桥接的核心逻辑芯片组的计算机系统和计算机系统存储器，其中图形地址重映射表（“GART表” ）由核心逻辑芯片组用于将AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的块或物理系统内存页来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向计算机系统物理存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联的图形数据页面的特征标志 。 其中一个特征标志被用作每个GART表条目的链接位，使得当核心逻辑芯片组读取存储在系统存储器中的GART表条目中的所选择的一个时，它将所选择的一个存储在其高速缓冲存储器中 并确定其链路位是否被设置。 如果所选择的第一个的链接位被设置，则所选择的一个的下一个被存储在高速缓冲存储器中，并且如果其链接位被设置，则所选择的一个的后续的一个被存储在高速缓冲存储器 直到其中一个链接位被确定为不被设置。

公开(公告)号：EP0902356A3

公开(公告)日：2000-01-12

申请号：EP98307111.9

申请日：1998-09-03

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Elliott, Robert C.

IPC: G06F3/14

CPC classification number: G09G5/39 ,  G06F3/14 ,  G06F12/1027 ,  G06F12/1081 ,  G09G5/363 ,  G09G2360/121 ,  G09G2360/125

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in the computer system physical memory, and feature flags that may be used to customize the associated page of graphics data. One of the feature flags is used as a link bit for each GART table entry such that when the core logic chipset reads selected ones of the GART table entries stored in the system memory, it stores a first one of the selected ones in its cache memory and determines if the link bit thereof is set. If the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in the cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in the cache memory until one of the link bits thereof is determined not to be set.

公开(公告)号：EP0902355A3

公开(公告)日：2000-01-12

申请号：EP98307097.0

申请日：1998-09-03

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Elliott, Robert C.

IPC: G06F3/14

CPC classification number: G06F3/14 ,  G06F12/1027 ,  G06F12/1081 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/125

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. A GART cache entry control register is used by an application programming interface, such as a GART miniport driver, to indicate to the core logic chipset that an individual GART table entry in the chipset cache should be invalidated and/or updated. The core logic chipset may then perform the required invalidate and/or update operation on the individual GART table entry without having to flush or otherwise disturb the other still relevant GART table entries stored in the cache.

公开(公告)号：EP0902355A2

公开(公告)日：1999-03-17

申请号：EP98307097.0

申请日：1998-09-03

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Elliott, Robert C.

IPC: G06F3/14

CPC classification number: G06F3/14 ,  G06F12/1027 ,  G06F12/1081 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/125

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. A GART cache entry control register is used by an application programming interface, such as a GART miniport driver, to indicate to the core logic chipset that an individual GART table entry in the chipset cache should be invalidated and/or updated. The core logic chipset may then perform the required invalidate and/or update operation on the individual GART table entry without having to flush or otherwise disturb the other still relevant GART table entries stored in the cache.

Abstract translation: 具有核心逻辑芯片组的计算机系统没有的功能上加速图形端口（“AGP”）总线装置之间的桥：诸如图形控制器，和一个主处理器和计算机系统存储器worin图形地址重映射表（“GART表” ）用于由所述核心逻辑芯片组以重新映射所使用的AGP图形控制器到物理存储器地址也驻留在计算机系统存储器的虚拟存储器地址。 所述GART表启用AGP图形控制器在连续的虚拟存储器地址空间的工作，但实际上使用非连续块或物理系统内存页来存储纹理，命令列表等。 所述GART表由条目的多个，每个条目包括地址指针的在存储器的图形数据的页面的基地址，并且功能标志也可以被用于定制相关的页面。 核心逻辑芯片组可以缓存最近使用GART表项的一个子集，以提高性能AGP在进行地址转换。 甲GART缓存条目控制寄存器在应用程序编程接口中所使用，检查作为GART微端口驱动程序，以指示核心逻辑芯片组在高速缓存中的芯片组个体GART表条目没有应该被无效和/或更新。 然后，将核心逻辑芯片组可以执行所需的无效和/或无需冲洗或以其他方式干扰存储在高速缓存中的其它无声相关GART表项更新在各个GART表条目的操作。