公开(公告)号：EP0924621A3

公开(公告)日：2000-06-28

申请号：EP98310482.9

申请日：1998-12-18

Applicant: Compaq Computer Corporation

Inventor： Elliott, Robert C. ,  Alzien, Khaldoun ,  Melo, Maria L. ,  Foster, Joseph E. ,  Fry, Walter G.

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1642 ,  G06F13/4031

Abstract: A computer system includes a bridge logic unit for interfacing between a microprocessor coupled to a processor bus, a first peripheral device coupled to a first peripheral bus such as a PCI bus, and a main memory coupled to a memory bus. Additional peripheral buses may further be connected to the bridge logic unit. The bridge logic unit includes a respective interface for each bus from which a memory request may be initiated. For example, the bridge logic unit may include a CPU interface configured to receive memory requests from the microprocessor, and a PCI interface configured to receive memory requests from a PCI bus peripheral. and an AGP interface configured to receive memory requests from an AGP/PCI bus peripheral. Additional interfaces are provided for any further buses supported by the system. A memory queue manager is coupled to receive memory requests from each of the interfaces and to provide the requests to a memory controller independent of the source of the request. In one embodiment, the memory queue manager includes a read request queue for receiving memory read requests, and a write request queue for receiving memory write requests. A queue arbiter is provided to arbitrate among requests from the various interfaces to determine a particular request which should be loaded within one of the queues (i.e., either the read request queue or the write request queue) of the memory queue manager. The queue arbiter is configured to take only a single request at a time from each interface. and implements a round-robin arbitration algorithm.

公开(公告)号：EP0924620A2

公开(公告)日：1999-06-23

申请号：EP98310413.4

申请日：1998-12-18

Applicant: Compaq Computer Corporation

Inventor： Maguire, David J. ,  Melo, Maria L. ,  Foster, Joseph E.

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4059

Abstract: A computer system includes a microprocessor coupled to a main memory through a bridge logic unit. The bridge logic unit receives memory read requests from the microprocessor and provides the requests to the main memory. The bridge logic unit includes a memory fetch control unit configured to fetch a single line of data from the main memory in response to an initial read request from the microprocessor. If a read request to a sequential line of data is received from the microprocessor, the memory fetch control unit fetches not only the requested line of data but also the next sequential line of data. Thus, following the initial read request in which a single line of data is fetched, when the microprocessor issues a request for data from a sequential line, that line is fetched and the subsequent line is speculatively prefetched. If the microprocessor continues with a request to yet an additional sequential line, the memory fetch unit continues its speculative generation of a request for the next sequential line. If the microprocessor issues a memory read request to a non-sequential line of data, the memory fetch control unit fetches only that line of data.

Abstract translation: 计算机系统包括通过桥逻辑单元耦合到主存储器的微处理器。 桥接逻辑单元从微处理器接收存储器读取请求并将该请求提供给主存储器。 桥逻辑单元包括存储器提取控制单元，其被配置为响应于来自微处理器的初始读取请求从主存储器获取单行数据。 如果从微处理器接收到对顺序数据行的读取请求，则存储器提取控制单元不仅获取所请求的数据行，而且还获取下一个顺序的数据行。 因此，在其中读取单行数据的初始读取请求之后，当微处理器从顺序行发出对数据的请求时，获取该行并且推测性地预取后续行。 如果微处理器继续请求另外的顺序行，则存储器提取单元继续对下一个顺序行的请求的推测生成。 如果微处理器向非连续数据行发出存储器读取请求，则存储器提取控制单元仅获取该数据行。

公开(公告)号：EP0924620A3

公开(公告)日：2000-06-28

申请号：EP98310413.4

申请日：1998-12-18

Applicant: Compaq Computer Corporation

Inventor： Maguire, David J. ,  Melo, Maria L. ,  Foster, Joseph E.

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4059

Abstract: A computer system includes a microprocessor coupled to a main memory through a bridge logic unit. The bridge logic unit receives memory read requests from the microprocessor and provides the requests to the main memory. The bridge logic unit includes a memory fetch control unit configured to fetch a single line of data from the main memory in response to an initial read request from the microprocessor. If a read request to a sequential line of data is received from the microprocessor, the memory fetch control unit fetches not only the requested line of data but also the next sequential line of data. Thus, following the initial read request in which a single line of data is fetched, when the microprocessor issues a request for data from a sequential line, that line is fetched and the subsequent line is speculatively prefetched. If the microprocessor continues with a request to yet an additional sequential line, the memory fetch unit continues its speculative generation of a request for the next sequential line. If the microprocessor issues a memory read request to a non-sequential line of data, the memory fetch control unit fetches only that line of data.

公开(公告)号：EP0924621A2

公开(公告)日：1999-06-23

申请号：EP98310482.9

申请日：1998-12-18

Applicant: Compaq Computer Corporation

Inventor： Elliott, Robert C. ,  Alzien, Khaldoun ,  Melo, Maria L. ,  Foster, Joseph E. ,  Fry, Walter G.

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1642 ,  G06F13/4031

Abstract: A computer system includes a bridge logic unit for interfacing between a microprocessor coupled to a processor bus, a first peripheral device coupled to a first peripheral bus such as a PCI bus, and a main memory coupled to a memory bus. Additional peripheral buses may further be connected to the bridge logic unit. The bridge logic unit includes a respective interface for each bus from which a memory request may be initiated. For example, the bridge logic unit may include a CPU interface configured to receive memory requests from the microprocessor, and a PCI interface configured to receive memory requests from a PCI bus peripheral. and an AGP interface configured to receive memory requests from an AGP/PCI bus peripheral. Additional interfaces are provided for any further buses supported by the system. A memory queue manager is coupled to receive memory requests from each of the interfaces and to provide the requests to a memory controller independent of the source of the request. In one embodiment, the memory queue manager includes a read request queue for receiving memory read requests, and a write request queue for receiving memory write requests. A queue arbiter is provided to arbitrate among requests from the various interfaces to determine a particular request which should be loaded within one of the queues (i.e., either the read request queue or the write request queue) of the memory queue manager. The queue arbiter is configured to take only a single request at a time from each interface. and implements a round-robin arbitration algorithm.

Abstract translation: 一种计算机系统，包括：用于耦合到一个处理器总线，耦合到第一外围总线的第一外围设备的微处理器之间的接口桥接逻辑单元：例如PCI总线，以及耦合到存储器总线的主存储器。 附加的外围总线可连接另外的桥接逻辑单元。 桥接逻辑单元包括用于从该存储器请求可被启动的每个总线一个respectivement接口。 对于实施例，桥接逻辑单元可以包括被配置为从所述微处理器接收的存储器请求CPU接口，并且被配置为接收来自PCI总线外围设备的存储器请求PCI接口。 和在AGP接口被配置为从在AGP / PCI总线外围设备接收存储器请求。 提供了额外的接口，用于由系统支持的任何进一步的总线。存储器队列管理器被耦合以接收来自每个接口的存储器请求，并提供请求到存储控制器独立于请求的来源的。 在一个中，实施例存储器队列管理器包括：用于接收存储器读取请求的读取请求队列，以及用于接收存储器写请求的写requestQueueLimit。 本发明提供一种仲裁器队列从各种接口请求之间进行仲裁，以确定地挖掘应的存储器队列管理器的队列（即，无论是读requestQueueLimit或写请求队列）中的一个内被加载特定的请求。 队列仲裁器被配置为采取只在来自各界面的时间的单个请求。 并实现了循环仲裁算法。