公开(公告)号：EP0820021A3

公开(公告)日：1998-01-28

申请号：EP97305239.2

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Maguire, David J. ,  Riley, Dwight D. ,  Edwards, James R.

IPC: G06F13/40

CPC classification number: G06F13/4045

Abstract: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

Abstract translation: 具有用于对接计算机系统的便携部分的扩展基座的计算机系统包括桥接电路，用于基于对接状态自适应解码总线上的地址。 扩展基座和便携式部分都包括桥接电路，用于将外围部件互连（PCI）总线的周期传递给工业标准体系结构（ISA）总线。 该桥包括用于控制解码的内部器件和配置寄存器。 用于连接到桥电路的各个ISA总线的内部设备和外部设备的总线周期被肯定解码。 取决于对接状态，未被正解码和声明的周期由桥电路之一进行减法解码。

公开(公告)号：EP0820021B1

公开(公告)日：2003-09-17

申请号：EP97305239.2

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Maguire, David J. ,  Riley, Dwight D. ,  Edwards, James R.

IPC: G06F13/40

CPC classification number: G06F13/4045

公开(公告)号：EP0902356A2

公开(公告)日：1999-03-17

申请号：EP98307111.9

申请日：1998-09-03

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Elliott, Robert C.

IPC: G06F3/14

CPC classification number: G09G5/39 ,  G06F3/14 ,  G06F12/1027 ,  G06F12/1081 ,  G09G5/363 ,  G09G2360/121 ,  G09G2360/125

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in the computer system physical memory, and feature flags that may be used to customize the associated page of graphics data. One of the feature flags is used as a link bit for each GART table entry such that when the core logic chipset reads selected ones of the GART table entries stored in the system memory, it stores a first one of the selected ones in its cache memory and determines if the link bit thereof is set. If the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in the cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in the cache memory until one of the link bits thereof is determined not to be set.

Abstract translation: 具有作为加速图形端口（“AGP”）总线设备（诸如图形控制器）和主机处理器之间的桥接的核心逻辑芯片组的计算机系统和计算机系统存储器，其中图形地址重映射表（“GART表” ）由核心逻辑芯片组用于将AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的块或物理系统内存页来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向计算机系统物理存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联的图形数据页面的特征标志 。 其中一个特征标志被用作每个GART表条目的链接位，使得当核心逻辑芯片组读取存储在系统存储器中的GART表条目中的所选择的一个时，它将所选择的一个存储在其高速缓冲存储器中 并确定其链路位是否被设置。 如果所选择的第一个的链接位被设置，则所选择的一个的下一个被存储在高速缓冲存储器中，并且如果其链接位被设置，则所选择的一个的后续的一个被存储在高速缓冲存储器 直到其中一个链接位被确定为不被设置。

公开(公告)号：EP0820021A2

公开(公告)日：1998-01-21

申请号：EP97305239.2

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Maguire, David J. ,  Riley, Dwight D. ,  Edwards, James R.

IPC: G06F13/40

CPC classification number: G06F13/4045

Abstract: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

Abstract translation: 具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。 扩展基座和便携式部分都包括用于将周期从外围部件互连（PCI）总线传递到工业标准架构（ISA）总线的桥接电路。 该桥包括用于控制解码的内部设备和配置寄存器。 用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。 取决于对接状态，桥接电路之一由一个桥接电路进行减法解码和声明的循环。

公开(公告)号：EP0902356A3

公开(公告)日：2000-01-12

申请号：EP98307111.9

申请日：1998-09-03

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Elliott, Robert C.

IPC: G06F3/14

CPC classification number: G09G5/39 ,  G06F3/14 ,  G06F12/1027 ,  G06F12/1081 ,  G09G5/363 ,  G09G2360/121 ,  G09G2360/125

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in the computer system physical memory, and feature flags that may be used to customize the associated page of graphics data. One of the feature flags is used as a link bit for each GART table entry such that when the core logic chipset reads selected ones of the GART table entries stored in the system memory, it stores a first one of the selected ones in its cache memory and determines if the link bit thereof is set. If the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in the cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in the cache memory until one of the link bits thereof is determined not to be set.

公开(公告)号：EP0902355A3

公开(公告)日：2000-01-12

申请号：EP98307097.0

申请日：1998-09-03

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Elliott, Robert C.

IPC: G06F3/14

CPC classification number: G06F3/14 ,  G06F12/1027 ,  G06F12/1081 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/125

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. A GART cache entry control register is used by an application programming interface, such as a GART miniport driver, to indicate to the core logic chipset that an individual GART table entry in the chipset cache should be invalidated and/or updated. The core logic chipset may then perform the required invalidate and/or update operation on the individual GART table entry without having to flush or otherwise disturb the other still relevant GART table entries stored in the cache.

公开(公告)号：EP0902355A2

公开(公告)日：1999-03-17

申请号：EP98307097.0

申请日：1998-09-03

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Elliott, Robert C.

IPC: G06F3/14

CPC classification number: G06F3/14 ,  G06F12/1027 ,  G06F12/1081 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/125

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. A GART cache entry control register is used by an application programming interface, such as a GART miniport driver, to indicate to the core logic chipset that an individual GART table entry in the chipset cache should be invalidated and/or updated. The core logic chipset may then perform the required invalidate and/or update operation on the individual GART table entry without having to flush or otherwise disturb the other still relevant GART table entries stored in the cache.

Abstract translation: 具有核心逻辑芯片组的计算机系统没有的功能上加速图形端口（“AGP”）总线装置之间的桥：诸如图形控制器，和一个主处理器和计算机系统存储器worin图形地址重映射表（“GART表” ）用于由所述核心逻辑芯片组以重新映射所使用的AGP图形控制器到物理存储器地址也驻留在计算机系统存储器的虚拟存储器地址。 所述GART表启用AGP图形控制器在连续的虚拟存储器地址空间的工作，但实际上使用非连续块或物理系统内存页来存储纹理，命令列表等。 所述GART表由条目的多个，每个条目包括地址指针的在存储器的图形数据的页面的基地址，并且功能标志也可以被用于定制相关的页面。 核心逻辑芯片组可以缓存最近使用GART表项的一个子集，以提高性能AGP在进行地址转换。 甲GART缓存条目控制寄存器在应用程序编程接口中所使用，检查作为GART微端口驱动程序，以指示核心逻辑芯片组在高速缓存中的芯片组个体GART表条目没有应该被无效和/或更新。 然后，将核心逻辑芯片组可以执行所需的无效和/或无需冲洗或以其他方式干扰存储在高速缓存中的其它无声相关GART表项更新在各个GART表条目的操作。