公开(公告)号：EP0667570A1

公开(公告)日：1995-08-16

申请号：EP95300924.8

申请日：1995-02-14

Applicant: Compaq Computer Corporation

Inventor： Ferguson, Patrick L. ,  Maguire, David J.

IPC: G06F7/00 ,  G06F5/06

CPC classification number: G06F5/10 ,  G06F7/00 ,  G06F2205/062

Abstract: In a computer system, a FIFO (first-in-first-out) queue is utilized to provide control information to the appropriate time slot in a time multiplexed serial link between an interface chip and a CODEC. The FIFO queue allows rewriting or replacement of any control registers present in the queue without requiring that a new entry be placed in the queue. A particular control register which is placed in the queue then maintains its place as the queue is emptied, even though the control register may be written one or more times while the control register entry is in the queue waiting for transmission to the CODEC. The loss of the prior command information is not a problem as the data rate of the serial link is still sufficiently high so that any minor transitory change which may have been desired would be of minimal effect in any regard and would have been inaudible to the human.

Abstract translation: 在计算机系统中，利用FIFO（先进先出）队列将控制信息提供给接口芯片和编解码器之间的时分复用串行链路中的适当时隙。 FIFO队列允许重写或替换队列中存在的任何控制寄存器，而不需要将新条目放置在队列中。 即使控制寄存器可能被写入一次或多次，而控制寄存器条目在等待传输到CODEC的队列中时，放置在队列中的特定控制寄存器就保持其位置。 丢失先前的命令信息不是问题，因为串行链路的数据速率仍然足够高，所以可能期望的任何轻微的瞬时变化在任何方面都将起到最小的影响，并且对于人类来说是不可听见的 。

公开(公告)号：EP0820021B1

公开(公告)日：2003-09-17

申请号：EP97305239.2

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Maguire, David J. ,  Riley, Dwight D. ,  Edwards, James R.

IPC: G06F13/40

CPC classification number: G06F13/4045

公开(公告)号：EP0924620A3

公开(公告)日：2000-06-28

申请号：EP98310413.4

申请日：1998-12-18

Applicant: Compaq Computer Corporation

Inventor： Maguire, David J. ,  Melo, Maria L. ,  Foster, Joseph E.

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4059

Abstract: A computer system includes a microprocessor coupled to a main memory through a bridge logic unit. The bridge logic unit receives memory read requests from the microprocessor and provides the requests to the main memory. The bridge logic unit includes a memory fetch control unit configured to fetch a single line of data from the main memory in response to an initial read request from the microprocessor. If a read request to a sequential line of data is received from the microprocessor, the memory fetch control unit fetches not only the requested line of data but also the next sequential line of data. Thus, following the initial read request in which a single line of data is fetched, when the microprocessor issues a request for data from a sequential line, that line is fetched and the subsequent line is speculatively prefetched. If the microprocessor continues with a request to yet an additional sequential line, the memory fetch unit continues its speculative generation of a request for the next sequential line. If the microprocessor issues a memory read request to a non-sequential line of data, the memory fetch control unit fetches only that line of data.

公开(公告)号：EP0820021A2

公开(公告)日：1998-01-21

申请号：EP97305239.2

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Santos, Gregory N. ,  Maguire, David J. ,  Riley, Dwight D. ,  Edwards, James R.

IPC: G06F13/40

CPC classification number: G06F13/4045

Abstract: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

Abstract translation: 具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。 扩展基座和便携式部分都包括用于将周期从外围部件互连（PCI）总线传递到工业标准架构（ISA）总线的桥接电路。 该桥包括用于控制解码的内部设备和配置寄存器。 用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。 取决于对接状态，桥接电路之一由一个桥接电路进行减法解码和声明的循环。

公开(公告)号：EP0820018A2

公开(公告)日：1998-01-21

申请号：EP97305238.4

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Riley, Dwight D. ,  Edwards, James R. ,  Maguire, David J.

IPC: G06F13/368 ,  G06F13/40

CPC classification number: G06F13/368

Abstract: An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

Abstract translation: 对于具有用于仲裁到总线的多个接入的多个仲裁器的计算机系统中的仲裁方案。 在优选实施例中，一种计算机系统被分为可拆卸膝上型部分，并且通过共享的PCI总线连接扩展基础单元上。 每个计算机系统的两个部分包括用于仲裁来自潜在PCI和ISA总线主机的PCI总线请求独立的PCI仲裁电路。 包括在计算机系统的各部分的膝上型内是顶部级别仲裁器做确定性地雷无论是在笔记本电脑或扩展基础单元的PCI仲裁器有权访问PCI总线。 无论是PCI仲裁者运行循环开始前，通常必须得到顶级仲裁者的资助。 而这些笔记本电脑对接，顶部级别仲裁的仲裁器PCI间上基本上时分多路复用的基础上选择。 而扩张基部和膝上型计算机被出坞，顶部级别仲裁器准许的总线访问到笔记本PCI仲裁器。

公开(公告)号：EP0784277A1

公开(公告)日：1997-07-16

申请号：EP96308940.4

申请日：1996-12-10

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Stevens, Jeffrey C. ,  Lester, Robert A. ,  Riley, Dwight D. ,  Maguire, David J. ,  Edwards, James R.

IPC: G06F13/28 ,  G06F13/12

CPC classification number: G06F13/28 ,  G06F13/126

Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Abstract translation: 一个计算机系统，在总线上具有独立但兼容的DMA控制器。 用于控制至少一个DMA通道的每个DMA控制器，每个DMA控制器具有用于执行DMA操作的独立的一组寄存器和用于指示通道状态和指定的配置寄存器。 DMA主机，用于与处理器进行兼容通信，并与多个DMA控制器进行初始化和通信。

公开(公告)号：EP0820022B1

公开(公告)日：2004-09-29

申请号：EP97305240.0

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Lin, Richard S. ,  Maguire, David J. ,  Edwards, James R. ,  Delisle, David J.

IPC: G06F13/40

CPC classification number: G06F13/4081 ,  G06F13/36

公开(公告)号：EP0820018A3

公开(公告)日：1999-03-10

申请号：EP97305238.4

申请日：1997-07-15

Applicant: Compaq Computer Corporation

Inventor： Riley, Dwight D. ,  Edwards, James R. ,  Maguire, David J.

IPC: G06F13/368 ,  G06F13/40

CPC classification number: G06F13/368

Abstract: An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

公开(公告)号：EP0784277B1

公开(公告)日：2003-03-05

申请号：EP96308940.4

申请日：1996-12-10

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Stevens, Jeffrey C. ,  Lester, Robert A. ,  Riley, Dwight D. ,  Maguire, David J. ,  Edwards, James R.

IPC: G06F13/28 ,  G06F13/12

CPC classification number: G06F13/28 ,  G06F13/126

公开(公告)号：EP0924620A2

公开(公告)日：1999-06-23

申请号：EP98310413.4

申请日：1998-12-18

Applicant: Compaq Computer Corporation

Inventor： Maguire, David J. ,  Melo, Maria L. ,  Foster, Joseph E.

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4059

Abstract: A computer system includes a microprocessor coupled to a main memory through a bridge logic unit. The bridge logic unit receives memory read requests from the microprocessor and provides the requests to the main memory. The bridge logic unit includes a memory fetch control unit configured to fetch a single line of data from the main memory in response to an initial read request from the microprocessor. If a read request to a sequential line of data is received from the microprocessor, the memory fetch control unit fetches not only the requested line of data but also the next sequential line of data. Thus, following the initial read request in which a single line of data is fetched, when the microprocessor issues a request for data from a sequential line, that line is fetched and the subsequent line is speculatively prefetched. If the microprocessor continues with a request to yet an additional sequential line, the memory fetch unit continues its speculative generation of a request for the next sequential line. If the microprocessor issues a memory read request to a non-sequential line of data, the memory fetch control unit fetches only that line of data.

Abstract translation: 计算机系统包括通过桥逻辑单元耦合到主存储器的微处理器。 桥接逻辑单元从微处理器接收存储器读取请求并将该请求提供给主存储器。 桥逻辑单元包括存储器提取控制单元，其被配置为响应于来自微处理器的初始读取请求从主存储器获取单行数据。 如果从微处理器接收到对顺序数据行的读取请求，则存储器提取控制单元不仅获取所请求的数据行，而且还获取下一个顺序的数据行。 因此，在其中读取单行数据的初始读取请求之后，当微处理器从顺序行发出对数据的请求时，获取该行并且推测性地预取后续行。 如果微处理器继续请求另外的顺序行，则存储器提取单元继续对下一个顺序行的请求的推测生成。 如果微处理器向非连续数据行发出存储器读取请求，则存储器提取控制单元仅获取该数据行。