公开(公告)号：EP0398191A3

公开(公告)日：1991-11-27

申请号：EP90108942.5

申请日：1990-05-11

Applicant: Compaq Computer Corporation

Inventor： Thoma, Roy E., III ,  Miller, Joseph P. ,  Skelton, Bill ,  Taylor, Mark ,  Bonella, Randy M.

IPC: G06F12/08

CPC classification number: G06F12/0886

Abstract: A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

Abstract translation: 64位宽的存储器通过32位数据总线进行多路复用，以将数据提供给由82385高速缓存控制器控制的64位线路大小的高速缓冲存储器。 所有64位存储器的存储器地址在整个传输过程中保持不变，以便发生零等待状态秒32位传输。 逻辑开发必要的下一个地址和就绪脉冲并阻止来自缓存控制器的这些信号。 逻辑还处理主存储器和高速缓存存储器的第2位地址。 主内存以分页模式运行，以进一步提高系统性能。

公开(公告)号：EP0398191A2

公开(公告)日：1990-11-22

申请号：EP90108942.5

申请日：1990-05-11

Applicant: Compaq Computer Corporation

Inventor： Thoma, Roy E., III ,  Miller, Joseph P. ,  Skelton, Bill ,  Taylor, Mark ,  Bonella, Randy M.

IPC: G06F12/08

CPC classification number: G06F12/0886

Abstract: A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

Abstract translation: 64位宽的存储器通过32位数据总线复用，以提供数据到由82385缓存控制器控制的64位行大小的高速缓冲存储器。 在整个传输过程中，保存所有64位存储器的存储器地址，从而发生零等待状态第二次32位传输。 逻辑开发所需的下一个地址和就绪脉冲，并从缓存控制器中阻止这些信号。 逻辑还处理主和高速缓冲存储器的位2地址。 主存储器以分页模式运行，以进一步提高系统性能。