公开(公告)号：EP0398191A3

公开(公告)日：1991-11-27

申请号：EP90108942.5

申请日：1990-05-11

Applicant: Compaq Computer Corporation

Inventor： Thoma, Roy E., III ,  Miller, Joseph P. ,  Skelton, Bill ,  Taylor, Mark ,  Bonella, Randy M.

IPC: G06F12/08

CPC classification number: G06F12/0886

Abstract: A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

Abstract translation: 64位宽的存储器通过32位数据总线进行多路复用，以将数据提供给由82385高速缓存控制器控制的64位线路大小的高速缓冲存储器。 所有64位存储器的存储器地址在整个传输过程中保持不变，以便发生零等待状态秒32位传输。 逻辑开发必要的下一个地址和就绪脉冲并阻止来自缓存控制器的这些信号。 逻辑还处理主存储器和高速缓存存储器的第2位地址。 主内存以分页模式运行，以进一步提高系统性能。

公开(公告)号：EP0398191A2

公开(公告)日：1990-11-22

申请号：EP90108942.5

申请日：1990-05-11

Applicant: Compaq Computer Corporation

Inventor： Thoma, Roy E., III ,  Miller, Joseph P. ,  Skelton, Bill ,  Taylor, Mark ,  Bonella, Randy M.

IPC: G06F12/08

CPC classification number: G06F12/0886

Abstract: A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

Abstract translation: 64位宽的存储器通过32位数据总线复用，以提供数据到由82385缓存控制器控制的64位行大小的高速缓冲存储器。 在整个传输过程中，保存所有64位存储器的存储器地址，从而发生零等待状态第二次32位传输。 逻辑开发所需的下一个地址和就绪脉冲，并从缓存控制器中阻止这些信号。 逻辑还处理主和高速缓冲存储器的位2地址。 主存储器以分页模式运行，以进一步提高系统性能。

公开(公告)号：EP0665500B1

公开(公告)日：2001-10-17

申请号：EP95300367.0

申请日：1995-01-20

Applicant: Compaq Computer Corporation

Inventor： Melo, Maria L. ,  Bonella, Randy M.

IPC: G06F13/364

CPC classification number: G06F13/364

公开(公告)号：EP0665500A1

公开(公告)日：1995-08-02

申请号：EP95300367.0

申请日：1995-01-20

Applicant: Compaq Computer Corporation

Inventor： Melo, Maria L. ,  Bonella, Randy M.

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

Abstract translation: 仲裁器允许重试请求在后续仲裁中具有高优先级，不会改变已授权但中止访问总线的优先级，但可以通过屏蔽其总线请求信号来阻止异常请求器抖动总线，直到数据可用。 此外，如果重试对主存储器的访问，则除了来自存储器系统的总线请求之外的所有总线请求都被屏蔽，以向存储器系统提供最高的有效优先级以允许发生任何刷新操作。 各种总线请求的屏蔽允许仲裁器控制对PCI标准总线的访问，而不需要添加特定的信号。 仲裁器还包括修改的优先级LRU技术，并且如果重试，则向锁定请求者提供附加的最高优先级位置。

公开(公告)号：EP0617365A1

公开(公告)日：1994-09-28

申请号：EP94302014.9

申请日：1994-03-22

Applicant: Compaq Computer Corporation

Inventor： Landry, John A. ,  Santeler, Paul A. ,  Thome, Gary W. ,  Bonella, Randy M. ,  Collins, Michael J.

IPC: G06F13/16

CPC classification number: G06F13/1615

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

Abstract translation: 一个内存控制器，最大限度地利用任何处理器流水线并同时运行大量的周期。 存储器控制器可以利用不同的速度存储器件并以其期望的最佳速度运行每个存储器件。 这些功能由多个简单的相互依赖的状态机执行，每个状态机负责整个操作的一小部分。 当每个状态机达到完成其功能时，它通知相关状态机现在可以继续进行，并继续等待下一个启动或继续指示。 下一台状态机以类似的方式运行。 负责一个周期的较早部分的状态机在下一个周期中开始执行任务，然后在负责周期的后期部分的状态机完成任务之前。 存储器控制器在逻辑上组织为三个主要块，前端块，存储块和主机块，每个都负责与其相关总线和组件的交互，并与各种其他块进行交互。 存储器控制器使用不同的速度存储器件，例如60ns和80ns，各个存储器件以其完全设计的速率工作。 存储器的速度是针对每个128K字节的存储器存储的，并且当发生存储器周期以重定向状态机时，使用该存储器的速度，从而实现存储器件的定时改变。

公开(公告)号：EP0617365B1

公开(公告)日：2001-06-13

申请号：EP94302014.9

申请日：1994-03-22

Applicant: Compaq Computer Corporation

Inventor： Landry, John A. ,  Santeler, Paul A. ,  Thome, Gary W. ,  Bonella, Randy M. ,  Collins, Michael J.

IPC: G06F13/16

CPC classification number: G06F13/1615

公开(公告)号：EP0665501A1

公开(公告)日：1995-08-02

申请号：EP95300369.6

申请日：1995-01-20

Applicant: Compaq Computer Corporation

Inventor： Bonella, Randy M. ,  Melo, Maria L.

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

Abstract translation: 仲裁器允许重试请求在随后的仲裁中具有高优先级，不通过对授予但中止的总线访问的优先级进行改变，而且防止被中止的请求者通过屏蔽其总线请求信号来捶打总线，直到数据可用。 此外，如果重新访问主存储器，则除了来自存储器系统的总线请求之外的所有总线请求都被屏蔽，以便为存储器系统提供最高的有效优先级，以允许发生任何冲洗操作。 各种总线请求的掩蔽允许仲裁器控制对PCI标准总线的访问，而不需要添加特定的信号。 仲裁者还包括修改的优先级LRU技术，并且如果重试则提供具有附加的，最优先位置的锁定请求者。