公开(公告)号：EP0428917A2

公开(公告)日：1991-05-29

申请号：EP90120911.4

申请日：1990-10-31

Applicant: Compaq Computer Corporation

Inventor： Hamid, Mustafa Ali ,  Thoma III, Roy E. ,  Thayer, John S.

IPC: G06F12/08

CPC classification number: G06F13/4243 ,  G06F12/0888

Abstract: A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with application software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to evaluate external addresses for a preset interval, preventing the processor from the accessing the cache, thereby slowing down the processor. The external address evaluation direction is released when a bus requesting device indicates a bus request during the slowdown, allowing the processor to respond to the bus request promptly to prevent possible latency problems from occurring, but still maintaining the processor in a halted state.

Abstract translation: 一种使用内部缓存降低高速微处理器的方法，以保持与为较慢速度微处理器编写的应用软件的兼容性。 处理器的内部高速缓存在减速期间无效，并且缓存地址比较电路用于以预设间隔评估外部地址，防止处理器访问高速缓存，从而减慢处理器的速度。 当总线请求设备在减速期间指示总线请求时，外部地址评估方向被释放，允许处理器迅速地响应总线请求，以防止发生可能的等待时间问题，但仍然使处理器处于停止状态。

公开(公告)号：EP0426386A2

公开(公告)日：1991-05-08

申请号：EP90311749.7

申请日：1990-10-26

Applicant: Compaq Computer Corporation

Inventor： Thayer, John S. ,  Mayer, Dale J. ,  Landry, John A. ,  Izquierdo, Javier F. ,  Culley, Paul R.

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F12/0653

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module (58) connected to a memory system. A RAM (126) is addressed by the system address lines defining 128 kbyte blocks, with the output data (TA, RASEN*) providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module (58). Various other parameters such as write protect status (HWP) and memory location (HLOCMEM*) are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

Abstract translation: 存储器映射和模块使能电路，用于允许为连接到存储器系统的任何模块（58）中的任何位置定义逻辑128K字节存储器块。 RAM（126）由定义128千字节块的系统地址线寻址，输出数据（TA，RASEN *）为特定存储器模块提供行地址选通使能信号，以及放置128千字节块所需的地址值 在模块（58）内。 RAM还提供了各种其他参数，如写保护状态（HWP）和存储器位置（HLOCMEM *）。 提供了编程和读取RAM的电路和技术。

公开(公告)号：EP0426329B1

公开(公告)日：1996-08-14

申请号：EP90311364.5

申请日：1990-10-17

Applicant: Compaq Computer Corporation

Inventor： Thayer, John S.

IPC: G06F13/42

CPC classification number: G06F13/4234

公开(公告)号：EP0426386A3

公开(公告)日：1992-11-25

申请号：EP90311749.7

申请日：1990-10-26

Applicant: Compaq Computer Corporation

Inventor： Thayer, John S. ,  Mayer, Dale J. ,  Landry, John A. ,  Izquierdo, Javier F. ,  Culley, Paul R.

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F12/0653

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module (58) connected to a memory system. A RAM (126) is addressed by the system address lines defining 128 kbyte blocks, with the output data (TA, RASEN*) providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module (58). Various other parameters such as write protect status (HWP) and memory location (HLOCMEM*) are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

公开(公告)号：EP0382469A3

公开(公告)日：1991-08-21

申请号：EP90301221.9

申请日：1990-02-06

Applicant: Compaq Computer Corporation

Inventor： Thayer, John S. ,  Culley, Paul R. ,  McGraw, Montgomery C.

IPC: G06F13/374

CPC classification number: G06F13/36 ,  G06F13/374

Abstract: A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems is described in which each processing module (12,12a) has a local cache (16,16a). Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibitied by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.

公开(公告)号：EP0307649A3

公开(公告)日：1990-08-08

申请号：EP88113497.7

申请日：1988-08-19

Applicant: Compaq Computer Corporation

Inventor： McGraw, Montgomery C. ,  Perez, Lazaro D. ,  Thayer, John S. ,  Bryant, Raymond J.

IPC: G06F12/06

CPC classification number: G06F12/063

Abstract: A data processing system is disclosed which permits the use of a memory mapped floating point coprocessor or other such peripheral, by a process which is unable to ad­dress the peripheral's resident memory location but which is able to address a specified location. Memory mapping means intercept attempted accesses by the process to the specified location and diverts the process's access in­struction to cause it to access the corresponding mapped address instead. An illustrative implementation is also described, namely the use of a Weitek 1167 memory-mapped, floating point coprocessor by processes running in the "virtual mode" of an Intel 80386 CPU.

公开(公告)号：EP0382469B1

公开(公告)日：1995-08-16

申请号：EP90301221.9

申请日：1990-02-06

Applicant: Compaq Computer Corporation

Inventor： Thayer, John S. ,  Culley, Paul R. ,  McGraw, Montgomery C.

IPC: G06F13/374

CPC classification number: G06F13/36 ,  G06F13/374

公开(公告)号：EP0428917A3

公开(公告)日：1991-10-23

申请号：EP90120911.4

申请日：1990-10-31

Applicant: Compaq Computer Corporation

Inventor： Hamid, Mustafa Ali ,  Thoma III, Roy E. ,  Thayer, John S.

IPC: G06F12/08

CPC classification number: G06F13/4243 ,  G06F12/0888

Abstract: A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with application software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to evaluate external addresses for a preset interval, preventing the processor from the accessing the cache, thereby slowing down the processor. The external address evaluation direction is released when a bus requesting device indicates a bus request during the slowdown, allowing the processor to respond to the bus request promptly to prevent possible latency problems from occurring, but still maintaining the processor in a halted state.

Abstract translation: 一种使用内部缓存降低高速微处理器的方法，以保持与为较慢速度微处理器编写的应用软件的兼容性。 处理器的内部高速缓存在减速期间无效，并且缓存地址比较电路用于以预设间隔评估外部地址，防止处理器访问高速缓存，从而减慢处理器的速度。 当总线请求设备在减速期间指示总线请求时，外部地址评估方向被释放，允许处理器迅速地响应总线请求，以防止发生可能的等待时间问题，但仍然使处理器处于停止状态。

公开(公告)号：EP0426329A1

公开(公告)日：1991-05-08

申请号：EP90311364.5

申请日：1990-10-17

Applicant: Compaq Computer Corporation

Inventor： Thayer, John S.

IPC: G06F13/42

CPC classification number: G06F13/4234

Abstract: A memory controller (48) of a personal computer has an asynchronous portion and a synchronous portion. The synchronous portion is used wher the system processor (20) is accessing the memory, while the asynchronous portion is used when control of the memories is held by a DMA controller (48) or a bus master (34) located on a standardised bus (44).

Abstract translation: 个人计算机的存储器控​​制器（48）具有异步部分和同步部分。 当系统处理器（20）正在访问存储器时使用同步部分，而当位于标准化总线上的DMA控制器（48）或总线主控器（34）保持存储器的控制时，使用异步部分 44）。

公开(公告)号：EP0382469A2

公开(公告)日：1990-08-16

申请号：EP90301221.9

申请日：1990-02-06

Applicant: Compaq Computer Corporation

Inventor： Thayer, John S. ,  Culley, Paul R. ,  McGraw, Montgomery C.

IPC: G06F13/374

CPC classification number: G06F13/36 ,  G06F13/374

Abstract: A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems is described in which each processing module (12,12a) has a local cache (16,16a). Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibitied by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.

Abstract translation: 描述了用于多处理器计算机系统的总线仲裁协议和伴随总线仲裁逻辑，其中每个处理模块（12,12a）具有本地高速缓存（16,16a）。 在有争议的设备上实施了几种总线仲裁政策，这些设备有效地将延迟状态引入到每个设备展示的仲裁行为中。 总线仲裁协议采用分布式仲裁控制方法，涉及仲裁设备的基本上固定的优先级排序。