公开(公告)号：EP0426161A3

公开(公告)日：1991-12-18

申请号：EP90120923.9

申请日：1990-10-31

Applicant: Compaq Computer Corporation

Inventor： Izquierdo, Javier F. ,  Landry, John A.

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F15/17 ,  G06F12/0284 ,  G06F12/0806

Abstract: A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

公开(公告)号：EP0426183A2

公开(公告)日：1991-05-08

申请号：EP90120980.9

申请日：1990-11-02

Applicant: Compaq Computer Corporation

Inventor： Melo, Maria L. ,  Landry, John A. ,  Culley, Paul R. ,  Goodrum, Alan L.

IPC: G06F13/42

CPC classification number: G06F13/4018 ,  G06F13/26 ,  G06F13/362 ,  G06F13/4072 ,  G06F13/409 ,  G06F13/423

Abstract: An apparatus for use in a computer system which delays operation when a wait signal is present, the apparatus providing a delay between back-to-back input/output cycles, the apparatus comprising: means for storing a programmed value that represents the length of delay to be provided between said back-to-back input/output cycles; means coupled to said storing means for producing a signal representing said length of delay; and means receiving said length of delay signal for generating the wait signal that delays the start of a successive inpt/output cycle for the length of time of said programmed delay.

Abstract translation: 一种在计算机系统中使用的装置，其在等待信号存在时延迟操作，所述装置在背靠背输入/输出周期之间提供延迟，所述装置包括：用于存储表示延迟长度的编程值的装置 在所述背对背输入/输出周期之间提供; 耦合到所述存储装置的装置，用于产生表示所述延迟长度的信号; 并且装置接收所述延迟信号的长度，用于产生延迟所述编程延迟的时间长度的连续输入/输出周期开始的等待信号。

公开(公告)号：EP0617365B1

公开(公告)日：2001-06-13

申请号：EP94302014.9

申请日：1994-03-22

Applicant: Compaq Computer Corporation

Inventor： Landry, John A. ,  Santeler, Paul A. ,  Thome, Gary W. ,  Bonella, Randy M. ,  Collins, Michael J.

IPC: G06F13/16

CPC classification number: G06F13/1615

公开(公告)号：EP0426183A3

公开(公告)日：1992-12-23

申请号：EP90120980.9

申请日：1990-11-02

Applicant: Compaq Computer Corporation

Inventor： Melo, Maria L. ,  Landry, John A. ,  Culley, Paul R. ,  Goodrum, Alan L.

IPC: G06F13/42

CPC classification number: G06F13/4018 ,  G06F13/26 ,  G06F13/362 ,  G06F13/4072 ,  G06F13/409 ,  G06F13/423

Abstract: An apparatus for use in a computer system which delays operation when a wait signal is present, the apparatus providing a delay between back-to-back input/output cycles, the apparatus comprising: means for storing a programmed value that represents the length of delay to be provided between said back-to-back input/output cycles; means coupled to said storing means for producing a signal representing said length of delay; and means receiving said length of delay signal for generating the wait signal that delays the start of a successive inpt/output cycle for the length of time of said programmed delay.

Abstract translation: 一种在计算机系统中使用的装置，其在等待信号存在时延迟操作，所述装置在背靠背输入/输出周期之间提供延迟，所述装置包括：用于存储表示延迟长度的编程值的装置 在所述背对背输入/输出周期之间提供; 耦合到所述存储装置的装置，用于产生表示所述延迟长度的信号; 并且装置接收所述延迟信号的长度，用于产生延迟所述编程延迟的时间长度的连续输入/输出周期开始的等待信号。

公开(公告)号：EP0843252A2

公开(公告)日：1998-05-20

申请号：EP97309013.7

申请日：1997-11-10

Applicant: Compaq Computer Corporation

Inventor： Tran, Thanh T. ,  Landry, John A. ,  Watts, Robert F.

IPC: G06F3/16

CPC classification number: G10H1/0058 ,  G10H2240/071

Abstract: An audio circuit for a computer includes a bidirectional modem connection, a microphone input, first and second audio output channels, and an audio synthesizing circuit arranged to produce first and second synthesized audio channels. In a first mode of operation the first synthesized audio channel is applied to the first audio output channel and the second synthesized audio channel is applied to the second audio output channel. In a second mode of operation the first and second synthesized audio channels are combined into a monotonic signal and applied to the second audio output channel, and audio signals from the bidirectional modem connection are applied to the first audio output channel.

Abstract translation: 一种用于计算机的音频电路包括双向调制解调器连接，麦克风输入，第一和第二音频输出通道以及被配置为产生第一和第二合成音频通道的音频合成电路。 在第一操作模式中，将第一合成音频通道应用于第一音频输出通道，并将第二合成音频通道应用于第二音频输出通道。 在第二操作模式中，第一和第二合成音频通道被组合成单调信号并被施加到第二音频输出通道，并且来自双向调制解调器连接的音频信号被施加到第一音频输出通道。

公开(公告)号：EP0431312A3

公开(公告)日：1991-12-11

申请号：EP90120909.8

申请日：1990-10-31

Applicant: Compaq Computer Corporation

Inventor： Landry, John A. ,  Culley, Paul R.

IPC: G06F13/24 ,  G06F15/16

CPC classification number: G06F13/26

Abstract: Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

公开(公告)号：EP0431312A2

公开(公告)日：1991-06-12

申请号：EP90120909.8

申请日：1990-10-31

Applicant: Compaq Computer Corporation

Inventor： Landry, John A. ,  Culley, Paul R.

IPC: G06F13/24 ,  G06F15/16

CPC classification number: G06F13/26

Abstract: Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

Abstract translation: 两个独立运行的微处理器共享共同的控制，数据和地址总线。 当总线上的第一个微处理器在总线上被分配时，通过在下一个总线周期开始时将中断向量放置在总线上来响应所有可屏蔽中断。 当第二个微处理器在总线上并且接收到可屏蔽的中断时，禁止下一个总线周期的开始，使中断向量放在总线上。

公开(公告)号：EP0426386A2

公开(公告)日：1991-05-08

申请号：EP90311749.7

申请日：1990-10-26

Applicant: Compaq Computer Corporation

Inventor： Thayer, John S. ,  Mayer, Dale J. ,  Landry, John A. ,  Izquierdo, Javier F. ,  Culley, Paul R.

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F12/0653

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module (58) connected to a memory system. A RAM (126) is addressed by the system address lines defining 128 kbyte blocks, with the output data (TA, RASEN*) providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module (58). Various other parameters such as write protect status (HWP) and memory location (HLOCMEM*) are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

Abstract translation: 存储器映射和模块使能电路，用于允许为连接到存储器系统的任何模块（58）中的任何位置定义逻辑128K字节存储器块。 RAM（126）由定义128千字节块的系统地址线寻址，输出数据（TA，RASEN *）为特定存储器模块提供行地址选通使能信号，以及放置128千字节块所需的地址值 在模块（58）内。 RAM还提供了各种其他参数，如写保护状态（HWP）和存储器位置（HLOCMEM *）。 提供了编程和读取RAM的电路和技术。

公开(公告)号：EP0843252A3

公开(公告)日：1999-06-30

申请号：EP97309013.7

申请日：1997-11-10

Applicant: Compaq Computer Corporation

Inventor： Tran, Thanh T. ,  Landry, John A. ,  Watts, Robert F.

IPC: G06F3/16

CPC classification number: G10H1/0058 ,  G10H2240/071

Abstract: An audio circuit for a computer includes a bidirectional modem connection, a microphone input, first and second audio output channels, and an audio synthesizing circuit arranged to produce first and second synthesized audio channels. In a first mode of operation the first synthesized audio channel is applied to the first audio output channel and the second synthesized audio channel is applied to the second audio output channel. In a second mode of operation the first and second synthesized audio channels are combined into a monotonic signal and applied to the second audio output channel, and audio signals from the bidirectional modem connection are applied to the first audio output channel.

公开(公告)号：EP0617365A1

公开(公告)日：1994-09-28

申请号：EP94302014.9

申请日：1994-03-22

Applicant: Compaq Computer Corporation

Inventor： Landry, John A. ,  Santeler, Paul A. ,  Thome, Gary W. ,  Bonella, Randy M. ,  Collins, Michael J.

IPC: G06F13/16

CPC classification number: G06F13/1615

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

Abstract translation: 一个内存控制器，最大限度地利用任何处理器流水线并同时运行大量的周期。 存储器控制器可以利用不同的速度存储器件并以其期望的最佳速度运行每个存储器件。 这些功能由多个简单的相互依赖的状态机执行，每个状态机负责整个操作的一小部分。 当每个状态机达到完成其功能时，它通知相关状态机现在可以继续进行，并继续等待下一个启动或继续指示。 下一台状态机以类似的方式运行。 负责一个周期的较早部分的状态机在下一个周期中开始执行任务，然后在负责周期的后期部分的状态机完成任务之前。 存储器控制器在逻辑上组织为三个主要块，前端块，存储块和主机块，每个都负责与其相关总线和组件的交互，并与各种其他块进行交互。 存储器控制器使用不同的速度存储器件，例如60ns和80ns，各个存储器件以其完全设计的速率工作。 存储器的速度是针对每个128K字节的存储器存储的，并且当发生存储器周期以重定向状态机时，使用该存储器的速度，从而实现存储器件的定时改变。