公开(公告)号：DE102005015789A1

公开(公告)日：2005-11-10

申请号：DE102005015789

申请日：2005-04-06

Applicant: ELPIDA MEMORY INC

Inventor： MICHIMATA SHIGETOMI ,  NAGAI RYO ,  YAMADA SATORU ,  NAKAMURA YOSHITAKA ,  NAKAMURA RYOICHI

IPC: H01L21/28 ,  H01L21/26 ,  H01L21/265 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/768 ,  H01L23/52 ,  H01L27/10 ,  H01L29/78

Abstract: A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p + diffused region; implanting indium into the surface of the p + diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.

公开(公告)号：JP2004087757A

公开(公告)日：2004-03-18

申请号：JP2002246287

申请日：2002-08-27

Applicant: Elpida Memory Inc ,  Hitachi Ltd ,  エルピーダメモリ株式会社 ,  株式会社日立製作所

Inventor： YAMADA SATORU ,  NAGAI AKIRA ,  OYU SHIZUNORI ,  NAKAMURA RYOICHI ,  TAKAURA NORIKATSU

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/10891 ,  H01L21/28061 ,  H01L21/823842 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4941 ,  H01L29/7833

Abstract: PROBLEM TO BE SOLVED: To provide a transistor, special to a DRAM (dynamic random access memory) for simultaneously achieving three points of improvement of the performance of a PMOS (p-channel metal oxide semiconductor) in the circumferential circuit of the DRAM, the reduction of a word line resistance and the mitigation of junction field of a memory cell.
SOLUTION: In the semiconductor device of a gate electrode structure consisting of three levels or more of Fermi level polysilicon, P-type polysilicon having the lowest Fermi level is arranged in a first N-type surface channel MOS (metal-oxide-semiconductor) transistor 13, N-type polysilicon having the highest Fermi level, is arranged in a second N-type surface channel MOS transistor 12 and the N-type polysilicon, having an intermediate Fermi level and produced through doping both of N-type impurities and P-type impurities, is arranged in a P-channel MOS transistor 11 respectively.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2005302757A

公开(公告)日：2005-10-27

申请号：JP2004111926

申请日：2004-04-06

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MICHIMATA SHIGEOMI ,  NAGAI AKIRA ,  YAMADA SATORU ,  NAKAMURA YOSHITAKA ,  NAKAMURA RYOICHI

IPC: H01L21/28 ,  H01L21/26 ,  H01L21/265 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/768 ,  H01L23/52 ,  H01L27/10 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/743 ,  H01L21/76805 ,  H01L21/76814 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a reduced contact resistance by forming a good titanium silicide layer even in a contact hole having a small diameter, and to provide its manufacturing method. SOLUTION: The method of manufacturing the semiconductor device comprises processes of forming a p + diffusion layer 14 by implanting boron into a surface region of a silicon substrate 11, forming an indium-doped layer 28 by implanting indium into a surface portion of the p + diffusion layer 14, forming a contact metal layer 18 on the indium-doped layer 28, and forming a titanium silicide layer 29 by letting the contact metal layer 18 and the silicon substrate 11 react with each other. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供即使在具有小直径的接触孔中形成良好的硅化钛层也具有降低的接触电阻的半导体器件，并且提供其制造方法。 解决方案：制造半导体器件的方法包括通过将硼注入到硅衬底11的表面区域中形成p + SP + +扩散层14的工艺，通过注入形成铟掺杂层28 铟进入p + 扩散层14的表面部分，在铟掺杂层28上形成接触金属层18，并通过使接触金属层18和 硅衬底11彼此反应。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2003347424A

公开(公告)日：2003-12-05

申请号：JP2002156605

申请日：2002-05-30

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKAMURA RYOICHI

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/808 ,  H01L29/861

CPC classification number: H01L29/8083 ,  H01L29/861

Abstract: PROBLEM TO BE SOLVED: To secure an electrical connection between a P well feeder diffusion layer region and a P well without increasing the number of processes, in a CMOS transistor. SOLUTION: The CMOS transistor has a PMOS transistor formation region A, an N well feeder diffusion layer region B, the P well feeder diffusion layer region C, and an NMOS transistor formation region D. In the NMOS transistor formation region D and the P well feeder diffusion layer region C, pocket boron implanted regions 104 implanted with pocket boron are formed. The P well 101 and the P well feeder diffusion region C are electrically connected by the pocket boron implanted regions. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：在CMOS晶体管中，为了确保P井供给器扩散层区域和P阱之间的电连接，而不增加处理次数。 解决方案：CMOS晶体管具有PMOS晶体管形成区域A，N阱馈送扩散层区域B，P阱馈送扩散层区域C和NMOS晶体管形成区域D.在NMOS晶体管形成区域D和 形成P阱供给扩散层区域C，注入了袋状硼的袋状硼注入区域104。 P阱101和P阱馈送扩散区C通过袋状硼注入区电连接。 版权所有（C）2004，JPO