公开(公告)号：DE102005015789A1

公开(公告)日：2005-11-10

申请号：DE102005015789

申请日：2005-04-06

Applicant: ELPIDA MEMORY INC

Inventor： MICHIMATA SHIGETOMI ,  NAGAI RYO ,  YAMADA SATORU ,  NAKAMURA YOSHITAKA ,  NAKAMURA RYOICHI

IPC: H01L21/28 ,  H01L21/26 ,  H01L21/265 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/768 ,  H01L23/52 ,  H01L27/10 ,  H01L29/78

Abstract: A method includes the steps of: implanting boron into a surface region of a silicon substrate to form a p + diffused region; implanting indium into the surface of the p + diffused region, to form an indium-implanted layer; forming a contact metal layer on the indium-implanted layer; and reacting silicon in the silicon substrate including the indium-implanted layer with metal in the contact metal layer to form a titanium silicide layer.

公开(公告)号：JP2011108927A

公开(公告)日：2011-06-02

申请号：JP2009263915

申请日：2009-11-19

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKAMURA YOSHITAKA ,  SUZUKI TAKAHIRO ,  NOMURA KAZUO ,  OTSUKA KEISUKE

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which can form a conductive film serving as a pseudo lower electrode and a lower electrode so as to enlarge the inner diameter of the lower electrode and can prevent the formation of a cavity in a region from a boundary area to a peripheral circuit area and respond to a demand for miniaturization.
SOLUTION: The manufacturing method of the semiconductor device includes a step of forming a cylinder hole 91 which defines the shape of a capacitor and a pseudo lower electrode groove 91a which defines the shape of the pseudo lower electrode 51a in an interlayer insulating film 24, a step of forming a conductive film 51b in the cylinder hole 91 and in the pseudo lower electrode groove 91a, a wet-etching step of performing wet-etching using the conductive film 51b as a stopper to remove the interlayer insulating film 24 formed at a memory cell region side of the pseudo lower electrode groove 91a, and a thinning step of thinning the conductive film 51b.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了提供可以形成用作伪下电极和下电极的导电膜的半导体器件的制造方法，以便扩大下电极的内径，并且可以防止形成 在从边界区域到外围电路区域的区域中的空腔，并且响应于对小型化的需求。 解决方案：半导体器件的制造方法包括形成限定电容器形状的气缸孔91和在下层绝缘膜中限定伪下电极51a的形状的伪下电极槽91a的步骤 如图24所示，在缸孔91和伪下电极槽91a中形成导电膜51b的步骤，使用导电膜51b作为阻挡层进行湿蚀刻的湿蚀刻步骤，以去除形成的层间绝缘膜24 在伪下电极槽91a的存储单元区域侧，以及使导电膜51b变薄的变薄步骤。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009054972A

公开(公告)日：2009-03-12

申请号：JP2007222932

申请日：2007-08-29

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MAEKAWA ATSUSHI ,  NAKAMURA YOSHITAKA

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/0207 ,  H01L27/10852

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method for further increasing the capacity of a capacitor by preventing lower electrodes from falling while suppressing bowing shapes of cylinder holes.
SOLUTION: The manufacturing method comprises processes of: forming a plurality of grooves on the surface layer of an inter-later insulating film after forming the inter-layer insulating film; forming buried insulating films 3 buried in the plurality of grooves; forming a plurality of cylinder holes arranged between the buried insulating films 3 of the inter-layer insulating film so as to be partially overlapped to the buried insulating films 3 arranged on both the sides; forming bottomed cylinder-shaped lower electrodes 5 each of which covers the bottom and side face of each cylinder hole; forming capacitor insulating films 6 for covering the surfaces of the lower electrodes 5 after removing the inter-layer insulating film; and forming an upper electrode 7 for covering surfaces on which the capacity insulating films 6 are formed.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体器件制造方法，用于通过防止下电极下降而进一步增加电容器的容量，同时抑制气缸孔的弯曲形状。 解决方案：制造方法包括以下处理：在形成层间绝缘膜之后，在后续绝缘膜的表面层上形成多个沟槽; 形成埋在所述多个槽中的埋入绝缘膜3; 在所述层间绝缘膜的所述埋入绝缘膜3之间形成多个气缸孔，以与设置在两侧的所述埋入绝缘膜3部分重叠; 形成有底筒状下部电极5，每个底部电极覆盖每个气缸孔的底部和侧面; 形成用于在去除层间绝缘膜之后覆盖下电极5的表面的电容器绝缘膜6; 并且形成用于覆盖其上形成有电容绝缘膜6的表面的上电极7。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007311610A

公开(公告)日：2007-11-29

申请号：JP2006140050

申请日：2006-05-19

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKAMURA YOSHITAKA ,  UNO TOMOHIRO

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L28/91

Abstract: PROBLEM TO BE SOLVED: To provide a capacitor with a less leakage current by restraining crystallization of a capacitive insulating film consisting of hafnium oxide and preventing deterioration of the capacitive insulating film caused by chlorine contained in an electrode.
SOLUTION: A tungsten nitride carbide (WNC) film, that is a material not containing a chlorine fraction in stock gas of film deposition, is used for upper and lower electrodes of a capacitor to form the upper or lower electrode in an amorphous state. The capacitive insulating film is formed in an amorphous state, and the formed capacitive insulating film is prevented from being crystallized upon heat treatment thereafter or from containing chlorine. A leakage current of a capacitor is reduced by preventing the crystallization of the capacitive insulating film and deterioration of the capacitive insulating film caused by containing chlorine.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：通过抑制由氧化铪组成的电容绝缘膜的结晶，并防止由电极中所含的氯引起的电容绝缘膜的劣化，来提供具有较少漏电流的电容器。 解决方案：在电容器的上部和下部电极中使用作为膜沉积的原料气体中不含氯部分的材料的氮化钨（WNC）膜，以形成无定形的上部或下部电极 州。 电容绝缘膜形成为非晶态，并且防止形成的电容绝缘膜在此后进行热处理或含有氯时结晶。 电容器的漏电流通过防止电容绝缘膜的结晶化以及由含氯引起的电容绝缘膜的劣化而降低。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2005302757A

公开(公告)日：2005-10-27

申请号：JP2004111926

申请日：2004-04-06

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MICHIMATA SHIGEOMI ,  NAGAI AKIRA ,  YAMADA SATORU ,  NAKAMURA YOSHITAKA ,  NAKAMURA RYOICHI

IPC: H01L21/28 ,  H01L21/26 ,  H01L21/265 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/768 ,  H01L23/52 ,  H01L27/10 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/743 ,  H01L21/76805 ,  H01L21/76814 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a reduced contact resistance by forming a good titanium silicide layer even in a contact hole having a small diameter, and to provide its manufacturing method. SOLUTION: The method of manufacturing the semiconductor device comprises processes of forming a p + diffusion layer 14 by implanting boron into a surface region of a silicon substrate 11, forming an indium-doped layer 28 by implanting indium into a surface portion of the p + diffusion layer 14, forming a contact metal layer 18 on the indium-doped layer 28, and forming a titanium silicide layer 29 by letting the contact metal layer 18 and the silicon substrate 11 react with each other. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供即使在具有小直径的接触孔中形成良好的硅化钛层也具有降低的接触电阻的半导体器件，并且提供其制造方法。 解决方案：制造半导体器件的方法包括通过将硼注入到硅衬底11的表面区域中形成p + SP + +扩散层14的工艺，通过注入形成铟掺杂层28 铟进入p + 扩散层14的表面部分，在铟掺杂层28上形成接触金属层18，并通过使接触金属层18和 硅衬底11彼此反应。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2008251763A

公开(公告)日：2008-10-16

申请号：JP2007090099

申请日：2007-03-30

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKAMURA YOSHITAKA ,  IZAWA MITSUTAKA

IPC: H01L21/8242 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10894

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device the flexibility of the layout of which can be assured by relaxing the density of first layer wiring, in which the parasitism resistor and the parasitism capacitance of the first layer wiring can be reduced, and which can be manufactured without any increase in the number of manufacturing steps, and its manufacturing method.
SOLUTION: There is provided the semiconductor device 10 in which a memory cell region and a peripheral circuit region are provided on a substrate. In the semiconductor device 10, assist wiring on the same layer as a landing pad 48 arranged for contact with a cell transistor on the bottom surface side of a capacitor of a memory cell region is provided on a peripheral circuit region or a border region of the memory cell region and the peripheral circuit region.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供半导体器件，可以通过放松第一层布线的密度来确保其布局的灵活性，其中寄生电阻器和第一层布线的寄生电容可以减小， 并且可以在不增加制造步骤的数量的情况下制造其制造方法。 解决方案：提供了其中在基板上设置存储单元区域和外围电路区域的半导体器件10。 在半导体装置10中，与存储单元区域的电容器的底面侧的与单电池晶体管接触的层叠焊盘48的同一层上的辅助布线设置在外围电路区域或边界区域 存储单元区域和外围电路区域。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008159988A

公开(公告)日：2008-07-10

申请号：JP2006349319

申请日：2006-12-26

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKAMURA YOSHITAKA ,  ARAO TAKASHI ,  MIYAHARA JIRO ,  ISHIKAWA SHIGEO ,  URABE KOJI

IPC: H01L21/8242 ,  H01L21/306 ,  H01L21/316 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L28/91

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a capacitor comprising a cylinder interlayer insulating film made of a two-layer interlayer insulating film, a charge storage capacitance of which is increased in the lower of a cylinder hole by making a hole diameter at the lower of the cylinder hole larger than the hole diameter at the upper, and moreover, a leakage current of which is low.
SOLUTION: An etching rate used for wet-etching of a first cylinder interlayer insulating film 23a is two times or higher, and lower than six times the etching rate used for wet-etching of a second cylinder interlayer insulating film 23b; the hole diameter of a first cylinder hole 50a is formed larger than the hole diameter of a second cylinder hole 50b; and the closer it is to a boundary 23c between the first cylinder interlayer insulating film 23a and the second cylinder interlayer insulating film 23b, the larger the hole diameter of the second cylinder hole 50b is formed in the vicinity of the boundary 23c.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有电容器的半导体器件，该电容器包括由双层层间绝缘膜制成的气缸层间绝缘膜，其电荷储存电容在气缸孔的下部增加， 气缸孔下部的孔直径大于上部的孔直径，另外漏电流低。 解决方案：用于第一气缸层间绝缘膜23a的湿蚀刻的蚀刻速率是第二气缸层间绝缘膜23b的湿蚀刻用蚀刻速度的两倍以上，低于六倍。 第一气缸孔50a的孔径形成为大于第二气缸孔50b的孔径; 并且越靠近第一气缸层间绝缘膜23a和第二气缸层间绝缘膜23b之间的边界23c，在边界23c附近形成第二气缸孔50b的孔径越大。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007305681A

公开(公告)日：2007-11-22

申请号：JP2006130527

申请日：2006-05-09

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKAMURA YOSHITAKA

IPC: H01L21/8242 ,  C23C16/14 ,  H01L21/3205 ,  H01L23/52 ,  H01L27/108

CPC classification number: H01L21/32051 ,  H01L27/10894 ,  H01L28/91

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which a landing pad to be connected with a lower electrode can be conveniently and easily formed when forming a capacitor for a semiconductor memory device.
SOLUTION: After a metal plug is formed in a contact hole of an insulating film, a selection CVD technology is used to grow a tungsten film in a self alignment manner with the metal plug to form a landing pad for each of the metal plugs. A lower electrode, a capacity insulating film, and an upper electrode are formed thereon in sequence.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造半导体器件的方法，当形成用于半导体存储器件的电容器时，能够方便且容易地形成与下部电极连接的层叠焊盘。 解决方案：在绝缘膜的接触孔中形成金属插塞之后，使用选择CVD技术以与金属插塞自对准的方式生长钨膜，以形成每个金属的着陆焊盘 塞。 依次形成下电极，电容绝缘膜和上电极。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2011086759A

公开(公告)日：2011-04-28

申请号：JP2009238238

申请日：2009-10-15

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKAMURA YOSHITAKA

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/0207 ,  H01L28/91

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of forming a lower electrode by a single film formation process for a conductive film, small in electric resistance of the lower electrode, improved in reliability, and reduced in manufacturing cost, and thereby to provide a semiconductor device large in contact areas between a capacitance insulating film, and lower and upper electrodes, and large in capacitor capacitance.
SOLUTION: After forming a first capacitor hole, a first mask material is embedded in an upper part of the first capacitor hole. A second capacitor hole is formed to be aligned with the first capacitor hole. After removing the first mask material, a lower electrode is formed in the first and second capacitor holes by a single film formation process. A capacitance insulating film and an upper electrode are sequentially formed on the lower electrode.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了提供能够通过用于导电膜的单一成膜工艺形成下电极的半导体器件，下电极的电阻小，可靠性提高并且制造成本降低，以及 从而提供在电容绝缘膜和下电极和上电极之间接触面积大的电容器电容量大的半导体器件。 解决方案：在形成第一电容器孔之后，第一掩模材料嵌入第一电容器孔的上部。 形成与第一电容器孔对准的第二电容器孔。 在去除第一掩模材料之后，通过单个成膜工艺在第一和第二电容器孔中形成下电极。 电容绝缘膜和上电极依次形成在下电极上。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010114133A

公开(公告)日：2010-05-20

申请号：JP2008283127

申请日：2008-11-04

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： NAKAMURA YOSHITAKA

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which has no problem of defect due to that a capacitor hole does not open in a process for forming a capacitor and no problem of contact between adjacent lower electrodes due to loss of a beam.
SOLUTION: A capacitor manufacturing process includes: a step of forming a long groove on inter-sacrificial layer insulation films 24a, b; a step of embedding a carbon film 81 into the long groove; a step of forming the capacitor hole on the carbon film 81; a step of forming a lower electrode 51 in the capacitor hole; and a step of removing the carbon film and the inter-sacrificial layer insulation film.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体器件的制造方法，该半导体器件由于在形成电容器的工艺中电容器孔不开放而没有缺陷，并且由于相邻的下部电极之间的接触问题， 梁的损失 电容器制造方法包括：在牺牲层间绝缘膜24a，b上形成长槽的步骤; 将碳膜81嵌入长槽的工序; 在碳膜81上形成电容器孔的工序; 在电容器孔中形成下部电极51的工序; 以及去除碳膜和牺牲牺牲层绝缘膜的步骤。 版权所有（C）2010，JPO＆INPIT