公开(公告)号：WO9940600A9

公开(公告)日：1999-11-25

申请号：PCT/US9902675

申请日：1999-02-10

Applicant: FED CORP

Inventor： MARINO JEFFREY R ,  HO JOSEPH K

IPC: H01J3/02 ,  H01J9/02 ,  H01L21/00

CPC classification number: H01J9/025 ,  H01J3/022

Abstract: Field emission devices may include emitter wells formed in a body of dielectric material. A gate conductor may be provided along the upper surface of the dielectric material. A gate hole may be provided in the gate conductor directly above each of the emitter wells. A method for forming the gate holes and emitter wells is disclosed. The method includes the steps of providing a first gate conductor layer on a dielectric layer. A pattern of second gate conductor material may be formed over the first gate conductor layer, said pattern defining gate holes in the second gate conductor material. The gate holes may then be completed and emitter wells formed by etching through the first gate conductor layer and into the dielectric layer using an etch that selectively etches the first gate conductor layer and the dielectric layer, and does not etch substantially the second gate conductor material.

Abstract translation: 场致发射器件可以包括在电介质材料体中形成的发射极阱。 栅极导体可以沿着介电材料的上表面设置。 可以在每个发射井正上方的栅极导体中提供栅极孔。 公开了一种形成栅孔和发射井的方法。 该方法包括在介电层上提供第一栅极导体层的步骤。 第二栅极导体材料的图案可以形成在第一栅极导体层上，所述图案在第二栅极导体材料中限定栅极孔。 然后可以完成栅极孔，并且通过使用选择性地蚀刻第一栅极导体层和介电层的蚀刻通过蚀刻穿过第一栅极导体层并进入介电层来形成发射极阱，并且基本不蚀刻第二栅极导体材料 。

公开(公告)号：WO9940600A2

公开(公告)日：1999-08-12

申请号：PCT/US9902675

申请日：1999-02-10

Applicant: FED CORP

Inventor： MARINO JEFFREY R ,  HO JOSEPH K

IPC: H01J3/02 ,  H01J9/02 ,  H01J

CPC classification number: H01J9/025 ,  H01J3/022

Abstract: Field emission devices may include emitter wells formed in a body of dielectric material. A gate conductor may be provided along the upper surface of the dielectric material. A gate hole may be provided in the gate conductor directly above each of the emitter wells. A method for forming the gate holes and emitter wells is disclosed. The method includes the steps of providing a first gate conductor layer on a dielectric layer. A pattern of second gate conductor material may be formed over the first gate conductor layer, said pattern defining gate holes in the second gate conductor material. The gate holes may then be completed and emitter wells formed by etching through the first gate conductor layer and into the dielectric layer using an etch that selectively etches the first gate conductor layer and the dielectric layer, and does not etch substantially the second gate conductor material.

Abstract translation: 场致发射器件可以包括在电介质材料体中形成的发射极阱。 可以沿着电介质材料的上表面设置栅极导体。 可以在每个发射极阱的正上方的栅极导体中设置栅极孔。 公开了一种用于形成栅极孔和发射极阱的方法。 该方法包括在电介质层上提供第一栅极导体层的步骤。 可以在第一栅极导体层之上形成第二栅极导体材料的图案，所述图案限定第二栅极导体材料中的栅极孔。 然后可以完成栅极孔，并且通过蚀刻通过第一栅极导体层并进入电介质层而形成的发射极阱，其使用选择性蚀刻第一栅极导体层和电介质层的蚀刻，并且基本不蚀刻第二栅极导体材料 。

公开(公告)号：WO9831044A3

公开(公告)日：1998-10-29

申请号：PCT/US9800149

申请日：1998-01-13

Applicant: FED CORP

Inventor： JONES GARY W ,  JONES SUSAN K S ,  MARINO JEFFREY ,  HO JOSEPH K ,  BOYSEL ROBERT MARK ,  ZIMMERMAN STEVEN M ,  LIU YACHIN ,  COSTA MICHAEL J ,  SILVERNAIL JEFFREY A

IPC: H01J1/304 ,  H01L

CPC classification number: H01J1/3042 ,  H01J2201/319 ,  H01J2329/00

Abstract: A field emitter device includes a column conductor (22), an insulator (23), and a resistor structure (32) for advantageously limiting current in a field emitter array. A wide column conductor (22) is deposited on an insulating substrate (21). An insulator (47) is laid over the column conductor (22). A high resistance layer (32) is placed on the insulator (23) and is physically isolated from the column conductor (22). The high resistance material may be chromium oxide or 10-50 wt.% Cr+SiO. A group of microtip electron emitters (30) is placed over the high resistance layer (32) to connect in an electrical series circuit the colum conductor (22), the high resistance layer (32), and the group of electron emitters (30). One or more layers of insulator (23) and a gate electrode (24), all with cavities for the electron emitters, are laid over the high resistance material (32). One layer of insulator is selected from a group of materials including SiC, SiO, and Si3N4. An anode plate (60) is attached with intermediate space (70) between the anode plate (60) and the microtip electron emitters (30) being evacuated.