公开(公告)号：WO9904407A3

公开(公告)日：1999-04-08

申请号：PCT/US9813695

申请日：1998-07-01

Applicant: FED CORP ,  LIU YACHIN ,  ZIMMERMAN STEVEN

Inventor： LIU YACHIN ,  ZIMMERMAN STEVEN

IPC: H01J1/304 ,  H01J1/02 ,  H01J1/16

CPC classification number: H01J1/3042 ,  H01J2201/319

Abstract: A current limiter for flat panel field emission display devices is disclosed. The current limiter includes a vertical resistor (22) and a lateral resistor (21) which in combination provide uniform emission and blow-out protection. The current limiter consists of two layers (21, 22) of different resistive materials. The resistivity for the top layer is determined by the emission current density requirement and the geometric configuration of the device, including emitter base and pitch dimensions, emitter density per array and the resistive film thickness. This top layer resistor conducts vertically and helps prevent emitters with slightly lower emission thresholds from delaying the turn-on of other emitters within a pixel. Intra-pixel individual emitter resistance is substantially controlled by the vertical resistive layer (22), while the blow-out resistance and inter-pixel uniformity is controlled primarily by the lateral resistive layer (21).

Abstract translation: 公开了一种用于平板场致发射显示装置的电流限制器。 电流限制器包括垂直电阻器（22）和横向电阻器（21），其组合提供均匀的发射和吹出保护。 电流限制器由不同电阻材料的两层（21,22）组成。 顶层的电阻率由发射电流密度要求和器件的几何配置决定，包括发射极基极和间距尺寸，每阵列的发射极密度和电阻膜厚度。 该顶层电阻器垂直传导，并有助于防止具有稍低的发射阈值的发射器延迟像素内的其它发射器的导通。 像素内的单个发射极电阻基本上由垂直电阻层（22）控制，而吹出电阻和像素间均匀性主要由横向电阻层（21）控制。

公开(公告)号：WO9831044A3

公开(公告)日：1998-10-29

申请号：PCT/US9800149

申请日：1998-01-13

Applicant: FED CORP

Inventor： JONES GARY W ,  JONES SUSAN K S ,  MARINO JEFFREY ,  HO JOSEPH K ,  BOYSEL ROBERT MARK ,  ZIMMERMAN STEVEN M ,  LIU YACHIN ,  COSTA MICHAEL J ,  SILVERNAIL JEFFREY A

IPC: H01J1/304 ,  H01L

CPC classification number: H01J1/3042 ,  H01J2201/319 ,  H01J2329/00

Abstract: A field emitter device includes a column conductor (22), an insulator (23), and a resistor structure (32) for advantageously limiting current in a field emitter array. A wide column conductor (22) is deposited on an insulating substrate (21). An insulator (47) is laid over the column conductor (22). A high resistance layer (32) is placed on the insulator (23) and is physically isolated from the column conductor (22). The high resistance material may be chromium oxide or 10-50 wt.% Cr+SiO. A group of microtip electron emitters (30) is placed over the high resistance layer (32) to connect in an electrical series circuit the colum conductor (22), the high resistance layer (32), and the group of electron emitters (30). One or more layers of insulator (23) and a gate electrode (24), all with cavities for the electron emitters, are laid over the high resistance material (32). One layer of insulator is selected from a group of materials including SiC, SiO, and Si3N4. An anode plate (60) is attached with intermediate space (70) between the anode plate (60) and the microtip electron emitters (30) being evacuated.