公开(公告)号：US20020125904A1

公开(公告)日：2002-09-12

申请号：US10062999

申请日：2002-01-30

Applicant: FormFactor, Inc.

Inventor： Benjamin N. Eldridge ,  Charles A. Miller

IPC: G01R031/26

CPC classification number: G01R31/31721 ,  G01R31/2851 ,  G01R31/31905 ,  G01R31/31924 ,  G06F1/26

Abstract: A power supply provides power to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal may temporarily increase due, for example, to state changes in the DUT. To limit variation (noise) in voltage at the power input terminal, a supplemental current is supplied to the power input terminal.

Abstract translation: 电源为被测集成电路设备（DUT）的电源端子供电。 DUT在电源输入端子上对电流的需求可能由于例如DUT的状态变化而暂时增加。 为了限制电源输入端子电压的变化（噪声），补充电流被提供给电源输入端子。

公开(公告)号：US20020036515A1

公开(公告)日：2002-03-28

申请号：US10003596

申请日：2001-10-30

Applicant: FORMFACTOR, INC.

Inventor： Benjamin N. Eldridge ,  Charles A. Miller

IPC: G01R031/26

CPC classification number: G06F1/26 ,  G01R31/31721 ,  Y10T307/50

Abstract: A main power supply continuously provides a current to a power input terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases during state changes in synchronous logic circuits implemented within the DUT. To limit variation (noise) in voltage at the power input terminal arising from these temporary increases in current demand, a charged capacitor is connected to the power input terminal during each DUT state change. The capacitor discharges into the power input terminal to supply additional current to meet the DUT's increased demand. Following each DUT state change the capacitor is disconnected from the power input terminal and charged to a level sufficient to meet a predicted increase in current demand during a next DUT state change.

公开(公告)号：US20040140822A1

公开(公告)日：2004-07-22

申请号：US10749358

申请日：2003-12-29

Applicant: FormFactor, Inc.

Inventor： Charles A. Miller

IPC: G01R001/00 ,  G01R031/02

CPC classification number: G01R1/073 ,  G01R1/06766 ,  G01R1/06772

Abstract: Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.

公开(公告)号：US20040046579A1

公开(公告)日：2004-03-11

申请号：US10430628

申请日：2003-05-05

Applicant: FormFactor, Inc.

Inventor： Matthew Chraft ,  Roy J. Henson ,  Charles A. Miller ,  Chih-Chiang Tseng

IPC: G01R031/02

CPC classification number: G01R1/07314 ,  G01R3/00

Abstract: A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads. A flex strip may alternatively be disposed behind a substrate with probes.

Abstract translation: 用于在集成电路（IC）测试器和要测试的IC的表面上的输入/输出，电源和接地焊盘之间提供信号路径的探针系统包括探针板组件，柔性电缆和一组探针， IC的I / O焊盘。 探针板组件包括一个或多个刚性衬底层，其具有形成在衬底层上或衬底层内的迹线和通孔，其提供将测试器连接到访问IC的一些衬垫的探针的相对低带宽的信号路径。 柔性电缆提供相对高带宽的信号路径，将测试仪连接到访问IC其他焊盘的探针。 柔性带可替代地设置在具有探针的基底之后。

公开(公告)号：US20030115568A1

公开(公告)日：2003-06-19

申请号：US10354636

申请日：2003-01-29

Applicant: FORMFACTOR, INC.

Inventor： Charles A. Miller ,  John M. Long

IPC: G06F017/50 ,  H03K017/693

CPC classification number: H01L24/49 ,  H01L23/5227 ,  H01L23/60 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/49113 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and its interconnect systems are designed by selecting and specifying interconnections between component cells included in the cell library. Interconnect systems are flexibily designed to act like filters tuned to optimize desired frequency response characteristics. Behavior models of the IC and its interconnect systems, based on the behavior models of their selected component, are subjected to simulation and verification tools to determine whether the IC and its interconnect systems meet various performance criteria and constraints. The structural models of the interconnect systems developed during the design process guide subsequent fabrication of interconnect systems for both the IC's intended testing and operating environments.

Abstract translation: 集成电路（IC）及其互连系统的设计方法包括IC元件单元和单元库中的互连元件单元。 每个IC组件单元提供可以并入到IC中的组件的物理和行为模型，而每个互连组件单元包括互连系统的单独的内部或外部组件的物理和行为模型，其可将IC连接到 外部节点。 通过选择和指定包含在单元库中的组件单元之间的互连来设计IC及其互连系统。 互连系统灵活设计为像调谐滤波器一样起作用，以优化所需的频率响应特性。 基于其所选组件的行为模型，IC及其互连系统的行为模型受到仿真和验证工具的影响，以确定IC及其互连系统是否符合各种性能标准和约束。 在设计过程中开发的互连系统的结构模型指导随后为IC的预期测试和操作环境制造互连系统。

公开(公告)号：US20040203262A1

公开(公告)日：2004-10-14

申请号：US10411175

申请日：2003-04-10

Applicant: FormFactor, Inc.

Inventor： Scott E. Lindsey ,  Charles A. Miller ,  David M. Royster ,  Stuart W. Wenzel

IPC: H01R012/00

CPC classification number: G01R1/06733 ,  G01R1/06711 ,  G01R1/06744 ,  G01R31/2884 ,  H01L21/4853 ,  H01L23/49811 ,  H01L2224/16 ,  H01L2924/00014 ,  H01R4/4863 ,  H01R12/57 ,  H01R13/035 ,  H01R13/2421 ,  H01R13/33 ,  H01R43/16 ,  H05K3/326 ,  H05K3/4007 ,  H05K3/4092 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/10265 ,  H05K2203/308 ,  H01L2224/0401

Abstract: A microelectronic spring contact for making electrical contact between a device and a mating substrate and method of making the same are disclosed. The spring contact has a compliant pad adhered to a substrate of the device and spaced apart from a terminal of the device. The compliant pad has a base adhered to the substrate, and side surfaces extending away from the substrate and tapering to a smaller end area distal from the substrate. A trace extends from the terminal of the device in a coil pattern over the compliant pad to its end area, forming a helix. At least a portion of the compliant pad end area is covered by the trace, and a portion of the trace that is over the compliant pad is supported by the compliant pad. In an alternative embodiment, the pad is removed to leave a freestanding helical contact.

Abstract translation: 公开了一种用于在器件和匹配衬底之间进行电接触的微电子弹簧触点及其制造方法。 弹簧触点具有粘附到装置的基板并与装置的端子间隔开的柔性衬垫。 柔性衬垫具有粘附到衬底的基底，以及远离衬底延伸的侧表面，并且逐渐变细到远离衬底的较小端部区域。 迹线从器件的端子以柔性衬垫的线圈图案延伸到其端部区域，形成螺旋线。 柔性焊盘端部区域的至少一部分被迹线覆盖，并且位于柔性焊盘上方的迹线的一部分由柔性焊盘支撑。 在替代实施例中，去除垫以留下独立的螺旋接触。

公开(公告)号：US20030237061A1

公开(公告)日：2003-12-25

申请号：US10177367

申请日：2002-06-19

Applicant: FormFactor, Inc.

Inventor： Charles A. Miller ,  Timothy Cooper ,  Yoshikazu Hatsukano

IPC: G06F017/50 ,  H01L029/40

CPC classification number: G11C29/56 ,  G01R31/2831 ,  G01R31/2886 ,  G01R31/31718 ,  G11C29/006 ,  G11C29/56016

Abstract: A semiconductor wafer is cut to singulate integrated circuit dice formed on the wafer. A die pick machine then positions and orients the singulated dice on a carrier base such that signal, power and ground pads formed on the surface of each die reside at predetermined positions relative to landmarks on the carrier base the die pick machine optically identifies. With the dice temporarily held in place on the carrier base, they are subjected to a series of testing and other processing steps. Since each die's signal pads reside in predetermined locations, they can be accessed by appropriately arranged probes providing test equipment with signal access to the pads during tests. After each test, a die pick machine may replace any die that fails the test with another die, thereby improving efficiency of subsequent testing and other processing resources.

Abstract translation: 切割半导体晶片以对形成在晶片上的集成电路芯片进行分割。 然后，骰子拾取机器将分离的骰子定位和定位在载体基座上，使得形成在每个模具表面上的信号，功率和接地垫相对于骰子拾取机器光学识别的载体基座上的标志位于预定位置。 将骰子临时固定在承运人基地上，对其进行一系列测试和其他处理步骤。 由于每个管芯的信号焊盘都位于预定位置，所以它们可以通过适当布置的探头进行访问，从而在测试期间为测试设备提供对焊盘的信号访问。 在每次测试之后，模具拾取机器可以用另一个模具代替未测试的任何模具，从而提高后续测试和其他处理资源的效率。

公开(公告)号：US20010035800A1

公开(公告)日：2001-11-01

申请号：US09805668

申请日：2001-03-13

Applicant: FORMFACTOR, INC.

Inventor： Charles A. Miller

IPC: H03H007/38

CPC classification number: G01R1/073 ,  G01R1/06766 ,  G01R1/06772

Abstract: Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.

Abstract translation: 这里描述的是提供用于在集成电路（IC）和IC测试仪的接合焊盘之间传送高频信号的信号路径的探针卡组件。 通过沿着信号路径适当地分布，调整和阻抗匹配电阻，电容和电感阻抗值来优化探针卡组件的频率响应，使得互连系统作为适当调节的巴特沃斯或切比雪夫滤波器。

公开(公告)号：US20030067316A1

公开(公告)日：2003-04-10

申请号：US10286062

申请日：2002-10-31

Applicant: FORMFACTOR, INC.

Inventor： Charles A. Miller

IPC: G01R031/02

CPC classification number: G01R1/073 ,  G01R1/06766 ,  G01R1/06772

Abstract: Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.

公开(公告)号：US20030006856A1

公开(公告)日：2003-01-09

申请号：US10211003

申请日：2002-08-02

Applicant: FORMFACTOR, INC.

Inventor： Charles A. Miller

IPC: H03H007/38

CPC classification number: H01L24/49 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/62 ,  H01L24/48 ,  H01L27/0248 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In an interconnect system for providing access to a common I/O terminal for multiple circuit devices such as drivers, receivers and electrostatic discharge (ESD) protection devices implemented on an IC, each such device is provided with a separate contact pad within the IC. The contact pads are linked to one another and to the IC I/O terminal though inductive conductors such as bond wires, metalization layer traces in the IC, or legs of a forked, lithographically-defined spring contact formed on the IC. The conductor inductance isolates the capacitance of the circuit devices from one another, thereby improving characteristics of the frequency response of the interconnect system. Also the ESD protection function is distributed among multiple ESD devices interconnected by series inductors to provide a multi-pole filter at each IC terminal. The inductances of the conductors and various capacitances of the interconnect system are also appropriately adjusted to optimize desired interconnect system frequency response characteristics.