公开(公告)号：WO2008076985B1

公开(公告)日：2008-08-28

申请号：PCT/US2007087801

申请日：2007-12-17

Applicant: WOJNAROWSKI ROBERT JOHN ,  GEN ELECTRIC ,  BERKAN ERTUGRUL ,  ANDARAWIS EMAD ANADARAWIS ,  SEALING CHARLES SCOTT ,  SEELY CHARLES SCOTT ,  DELGADO ELADIO CLEMENTE ,  HAYS DAVID CECIL ,  KAPUSTA CHRISTOPHER JAMES ,  GRUBER NANETTE JUDITH

Inventor： BERKAN ERTUGRUL ,  ANDARAWIS EMAD ANADARAWIS ,  SEALING CHARLES SCOTT ,  SEELY CHARLES SCOTT ,  DELGADO ELADIO CLEMENTE ,  HAYS DAVID CECIL ,  KAPUSTA CHRISTOPHER JAMES ,  GRUBER NANETTE JUDITH

IPC: H01L27/20 ,  G01N29/14 ,  G01N29/22 ,  H01L41/04 ,  H01L41/113

CPC classification number: H01L27/20 ,  G01M5/00 ,  G01N29/245 ,  G01N29/2475 ,  G01N2291/0231 ,  H01L41/047 ,  H01L41/1132

Abstract: A piezoelectric planar composite apparatus (30, 30') to provide health monitoring of a structure and associated methods are provided. The piezoelectric planar composite apparatus (30, 30') includes a piezoelectric electric material layer (41, 41'), multiple electrodes (35, 35') positioned in electrical contact with the piezoelectric material layer (41, 41'), and multiple sets of electrode interconnect conductors (53) each positioned in electrical contact with a different subset of the of the electrodes (35, 35') and positioned to form multiple complementary electrode patterns. Each of the complementary electrode patterns is positioned to form an electric field having an electric field axis oriented along a different physical axis from that of an electric field formed by at least one other of the complementary electrode patterns. The interconnect conductors (53) can be distributed over several electrode interconnect conductor carrying layers (51) to enhance formation of the different complementary electrode patterns.

Abstract translation: 提供了一种用于提供对结构和相关方法的健康监测的压电平面复合设备（30,30'）。 压电平面复合设备（30,30'）包括压电电材料层（41,41'），定位成与压电材料层（41,41'）电接触的多个电极（35,35'），以及多个 电极互连导体组（53），每个电极互连导体定位成与电极（35,35'）的不同子集电接触并定位以形成多个互补电极图案。 互补电极图案中的每一个被定位为形成电场，该电场具有沿着与由互补电极图案中的至少一个另外的互补电极图案形成的电场不同的物理轴定向的电场轴。 互连导体（53）可以分布在几个电极互连导体承载层（51）上以增强不同互补电极图案的形成。

公开(公告)号：CA2641081A1

公开(公告)日：2009-04-24

申请号：CA2641081

申请日：2008-10-16

Applicant: GEN ELECTRIC

Inventor： SUBRAMANIAN KANAKASABAPATHI ,  BOOMHOWER OLIVER CHARLES ,  HAYS DAVID CECIL ,  CLAYDON GLENN SCOTT ,  KEIMEL CHRISTOPHER FRED ,  AIMI MARCO FRANCESCO

IPC: B81B7/02 ,  B81B3/00 ,  B81B7/04

Abstract: An electrical through-connection, or via, that passes through a substrate (2 2) to a bus (28) on a first surface (21) of the substrate (22). The via may be configured with an interlock (46) such that the electrically conductive core (60) of th e via is constrained to thermally expand towards the second surface (23), away from t he bus (28), thus preventing damage to the bus (28). The interlock (46) may be a local constriction or enlargement of the via near the first surface (21) of the substrate (22). The via may be greater in length along the bus (28) than a unit spacing of beams (30) in a parallel microswitch array (20) actuated in unison along the bus (28). The via may be narrower in width than in length, and may form a trapezoidal geometry that is larger at the second surface (23) of the substrate (22) than at the first surface (21).

公开(公告)号：CA2640827A1

公开(公告)日：2009-04-15

申请号：CA2640827

申请日：2008-10-09

Applicant: GEN ELECTRIC

Inventor： AIMI MARCO FRANCESCO ,  GOWDA ARUN VIRUPAKSHA ,  KAPUSTA CHRISTOPHER JAMES ,  CLAYDON GLENN SCOTT ,  HAYS DAVID CECIL ,  BOOMHOWER OLIVER CHARLES ,  KEIMEL CHRISTOPHER FRED ,  IANNOTTI JOSEPH ALFRED

IPC: B81B7/02 ,  B81C99/00

Abstract: Multiple microelectromechanical systems (MEMS) on a substrate (20) are capped with a cover (28) using a layer that may function as a bonding agent, separation layer, and hermetic seal. A substrate (20) has a first side (20A) with multiple MEMS devices. A cover (28) is formed with through-holes (40) for vi as (40), and with standoff posts (34) for layer registration and separation. An adhesive sheet (42) is patterned with cutouts (44) for the MEMS devices, vias (40), a nd standoff posts (34). The adhesive sheet (42) is tacked to the cover (28), th en placed on the mems substrate (20) and heated to bond the layers. The via holes (40) may be metalized with leads for circuit board (58) connection. The mems units (22) may be diced from the substrate (20) after sealing, thus protecting them from contaminants.