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公开(公告)号:US20210066126A1
公开(公告)日:2021-03-04
申请号:US16556465
申请日:2019-08-30
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Eswar Ramanathan , Sunil Kumar Singh , Xuan Anh Tran , Suryanarayana Kalaga , Juan Boon Tan
IPC: H01L21/768 , H01L27/22 , H01L43/02 , H01L43/12 , H01L27/24 , H01L45/00 , H01L27/11507
Abstract: One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.
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公开(公告)号:US11515205B2
公开(公告)日:2022-11-29
申请号:US16556465
申请日:2019-08-30
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Eswar Ramanathan , Sunil Kumar Singh , Xuan Anh Tran , Suryanarayana Kalaga , Juan Boon Tan
IPC: H01L21/768 , H01L27/22 , H01L43/02 , H01L43/12 , H01L27/11507 , H01L45/00 , H01L27/24
Abstract: One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.
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公开(公告)号:US11367750B2
公开(公告)日:2022-06-21
申请号:US16439101
申请日:2019-06-12
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Sunil Kumar Singh , Xuan Anh Tran , Eswar Ramanathan , Suryanarayana Kalaga , Craig M. Child , Robert Fox
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.
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公开(公告)号:US11094585B2
公开(公告)日:2021-08-17
申请号:US16504737
申请日:2019-07-08
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Xuan Anh Tran , Eswar Ramanathan , Sunil Kumar Singh , Suryanarayana Kalaga , Suresh Kumar Regonda , Juan Boon Tan
IPC: H01L21/768 , H01L23/535 , H01L43/02 , H01L45/00 , H01L27/22 , H01L27/11502 , H01L43/12
Abstract: One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.
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