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    GENERATING PEER-TO-PEER NETWORK ADDRESSES
    1.
    发明申请
    GENERATING PEER-TO-PEER NETWORK ADDRESSES 审中-公开
    生成对等网络地址

    公开(公告)号：WO2017123253A1

    公开(公告)日：2017-07-20

    申请号：PCT/US2016/013686

    申请日：2016-01-15

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： HANSEN, Peter ,  RAYMOND, Patrick A.

    IPC: H04L29/12 ,  H04L12/40 ,  G06F13/42

    CPC classification number: G06F13/42 ,  H04L12/40 ,  H04L61/2038 ,  H04L61/6004 ,  H04L61/6022

    Abstract: An apparatus includes a module to interface to a network bus. A module descriptor specifies functionality of the module. A port on the module connects to a mating connector and receives a slot location where the module is connected. A controller generates a peer-to-peer network address for the module to communicate on the network bus. The peer-to-peer network address incorporates the module descriptor and the slot location to generate a unique network address for the network bus. The peer-to-peer network address enables other peer modules on the network bus to communicate directly with the module.

    Abstract translation: 一种装置包括与网络总线接口的模块。 模块描述符指定模块的功能。 模块上的端口连接到配对连接器，并接收模块连接的插槽位置。 控制器生成模块在网络总线上进行通信的点对点网络地址。 对等网络地址包含模块描述符和插槽位置，为网络总线生成唯一的网络地址。 对等网络地址使网络总线上的其他对等模块能够直接与模块通信。

    PRESERVING VOLATILE MEMORY ACROSS A COMPUTER SYSTEM DISRUPTION
    2.
    发明申请
    PRESERVING VOLATILE MEMORY ACROSS A COMPUTER SYSTEM DISRUPTION 审中-公开
    通过计算机系统故障保存挥发性记忆

    公开(公告)号：WO2017014793A1

    公开(公告)日：2017-01-26

    申请号：PCT/US2015/041815

    申请日：2015-07-23

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： FEVRIER, Thierry ,  VALDEZ, David C. ,  RAYMOND, Patrick A. ,  PARK, Justin Haanbyull ,  MOHR, David P. ,  NGUYEN, Hai Ngoc ,  MCGOWEN, Michael Edward

    IPC: G06F12/16 ,  G06F12/02

    CPC classification number: G06F12/16 ,  G06F11/1441 ,  G06F11/1446 ,  G06F11/2015

    Abstract: A method for preserving volatile memory across a computer system disruption includes identifying a set of volatile memory. The set of volatile memory represents a portion of data in volatile memory to preserve during a system disruption. The method includes receiving a system event. The system event indicates that a computer system disruption will occur and that the set of volatile memory is to be written to a stable storage device. The method includes writing the set of volatile memory to the stable storage device to create a stored data set.

    Abstract translation: 用于在计算机系统中保持易失性存储器的方法中断包括识别一组易失性存储器。 该组易失性存储器表示在系统中断期间保存的易失性存储器中的一部分数据。 该方法包括接收系统事件。 系统事件表示将发生计算机系统中断，并将该组易失性存储器写入稳定的存储设备。 该方法包括将易失性存储器集合写入稳定存储设备以创建存储的数据集。

    DATA WRITE BACK
    3.
    发明申请
    DATA WRITE BACK 审中-公开
    数据写回

    公开(公告)号：WO2016076850A1

    公开(公告)日：2016-05-19

    申请号：PCT/US2014/065193

    申请日：2014-11-12

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： RAYMOND, Patrick A. ,  DENEUI, Nathan S. ,  FOTHERGILL, Dennis W.

    IPC: G06F1/26 ,  H02J9/06

    CPC classification number: G06F1/30

    Abstract: Example implementations relate to data write back. For example, a data write back system, comprising a micro-uninterruptible power supply (µUPS) module to signal a primary power supply interruption to a controller, and the controller to segregate a portion of memory, and restore data to the segregated portion of memory in response to the primary power supply interruption signal.

    Abstract translation: 示例实现涉及回写数据。 例如，一种数据回写系统，包括用于向控制器发出主电源中断的微不间断电源（μUPS）模块，以及控制器分离存储器的一部分，并将数据恢复到存储器的分离部分 响应于主电源中断信号。

    A NETWORKING INFRASTRUCTURE CENTER
    4.
    发明申请
    A NETWORKING INFRASTRUCTURE CENTER 审中-公开
    网络基础设施中心

    公开(公告)号：WO2017023247A1

    公开(公告)日：2017-02-09

    申请号：PCT/US2015/043131

    申请日：2015-07-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： RAYMOND, Patrick A. ,  SABOTTA, Michael L. ,  BENEDICT, Melvin K. ,  WANG, Han

    IPC: H04L12/931 ,  H04L29/04

    CPC classification number: H04L29/04 ,  H04L49/10 ,  H04L49/15 ,  H04L49/356 ,  H04L49/65

    Abstract: A networking infrastructure center includes a networking chassis, networking switches implemented in the networking chassis via module slots, the networking switches being swappable in the module slots to create an infrastructure topology, storage switches implemented in the networking chassis via the module slots, the storage switches being swappable to create the infrastructure topology, and a shuffler, the shuffler to detect locations of the networking switches and the storage switches to allow the networking switches and the storage switches to be placed in arbitrary locations on the networking chassis and to realize the infrastructure topology by splitting the infrastructure topology via physical signal multiplexing to physically isolate the networking switches and the storage switches.

    Abstract translation: 网络基础设施中心包括网络机箱，通过模块插槽在网络机箱中实现的网络交换机，网络交换机可在模块插槽中交换以创建基础架构拓扑，通过模块插槽实现在网络机箱中的存储交换机，存储交换机 可交换以创建基础架构拓扑，以及一个洗牌器，该洗牌器检测网络交换机和存储交换机的位置，以允许网络交换机和存储交换机放置在网络机箱上的任意位置，并实现基础架构拓扑 通过物理信号复用将基础架构拓扑分解，以物理隔离网络交换机和存储交换机。

    ERASURE MULTI-CHECKSUM ERROR CORRECTION CODE
    7.
    发明申请
    ERASURE MULTI-CHECKSUM ERROR CORRECTION CODE 审中-公开
    ERASURE MULTI-CHECKSUM错误修正代码

    公开(公告)号：WO2016122515A1

    公开(公告)日：2016-08-04

    申请号：PCT/US2015/013460

    申请日：2015-01-29

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： WANG, Han ,  RAYMOND, Patrick A. ,  VENUGOPAL, Raghavan V.

    IPC: G11C29/42

    CPC classification number: G11C16/3445 ,  G11C29/42 ,  G11C29/52

    Abstract: A system includes a plurality of memory of devices to store data. The system further includes a parity generation module including a checksum module to perform a checksum operation on each row of data in each of the plurality of memory devices to provide respective checksum outputs. The parity generation module further comprises an erasure parity module to perform an erasure parity operation on each column of data in each of the plurality of memory devices to provide respective erasure parity outputs. The parity generation module can evaluate the checksum output and the erasure parity output for each of the plurality of memory devices to provide parity data to indicate whether a given memory device of the plurality of memory devices contains an error.

    Abstract translation: 系统包括用于存储数据的设备的多个存储器。 该系统还包括奇偶校验生成模块，其包括校验和模块，以对多个存储器设备中的每一个中的每一行数据执行校验和操作，以提供相应的校验和输出。 奇偶校验生成模块还包括擦除奇偶校验模块，用于对多个存储器件中的每一个中的每列数据执行擦除奇偶校验操作，以提供相应的擦除奇偶校验输出。 奇偶校验生成模块可以评估多个存储器件中的每一个的校验和输出和擦除奇偶校验输出，以提供奇偶校验数据，以指示多个存储器件中的给定存储器件是否包含错误。

    FORMING A RECESS IN A MULTI-LAYERED DEVICE
    8.
    发明申请
    FORMING A RECESS IN A MULTI-LAYERED DEVICE 审中-公开
    在多层设备中形成记忆

    公开(公告)号：WO2016114775A1

    公开(公告)日：2016-07-21

    申请号：PCT/US2015/011434

    申请日：2015-01-14

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： KAPOOR, Mark V. ,  ENGLER, David W. ,  RAYMOND, Patrick A.

    IPC: H05K3/46

    CPC classification number: H05K1/183 ,  H05K1/0298 ,  H05K2201/1003

    Abstract: A method related to removing layers in a multi-layered PCB is described. The method includes removing one of more layers of a multi-layered printed circuit board (PCB) layer via material removal techniques. The removal of the layers reduces the thickness of the multi-layered PCB in a section while the thickness in another section of the PCB is maintained. The method includes forming a recess in the section of the multi-layered PCB to provide additional spacing on the multi-layered PCB. The method further includes placing components in the recessed section of the multi-layered PCB.

    Abstract translation: 描述了涉及去除多层PCB中的层的方法。 该方法包括通过材料去除技术去除多层印刷电路板（PCB）层中的多层。 这些层的去除减少了部分中多层PCB的厚度，同时保持了PCB的另一部分中的厚度。 该方法包括在多层PCB的部分中形成凹槽，以在多层PCB上提供额外的间隔。 该方法还包括将组件放置在多层PCB的凹陷部分中。

    BACKUP POWER SUPPLY CELL IN MEMORY DEVICE
    9.
    发明申请
    BACKUP POWER SUPPLY CELL IN MEMORY DEVICE 审中-公开
    备份存储设备中的电源单元

    公开(公告)号：WO2016069003A1

    公开(公告)日：2016-05-06

    申请号：PCT/US2014/063490

    申请日：2014-10-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： NGUYEN, Hai Ngoc ,  WANG, Han ,  RAYMOND, Patrick A. ,  VENUGOPAL, Raghavan V.

    IPC: G11C5/14 ,  G06F1/30 ,  H02J9/00

    CPC classification number: G11C5/141 ,  G06F1/263 ,  G11C5/04 ,  H02J9/061

    Abstract: Example implementations relate to a backup power supply in a memory cell. For example, a parallel backup power supply system can include a memory device. The memory device can include memory that is integrated in the memory device. The memory device can also include a back-up power supply cell that is integrated in the memory device and that provides back-up power supply to the memory.

    Abstract translation: 示例实现涉及存储器单元中的备用电源。 例如，并行备用电源系统可以包括存储器设备。 存储器件可以包括集成在存储器件中的存储器。 存储器件还可以包括集成在存储器件中并且为存储器提供备用电源的备用电源单元。

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