公开(公告)号：WO2019212488A1

公开(公告)日：2019-11-07

申请号：PCT/US2018/030219

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： CHALAMALASETTI, Sai Rahul ,  FARABOSCHI, Paolo ,  FOLTIN, Martin ,  GRAVES, Catherine ,  MILOJICIC, Dejan S. ,  STRACHAN, John Paul ,  SEREBRYAKOV, Sergey

IPC: G11C13/00

Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

公开(公告)号：WO2019212466A1

公开(公告)日：2019-11-07

申请号：PCT/US2018/030125

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： STRACHAN, John Paul ,  MILOJICIC, Dejan S. ,  FOLTIN, Martin ,  CHALAMALASETTI, Sai Rahul ,  SHARMA, Amit S.

IPC: G06F15/78 ,  G06F15/163

Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

公开(公告)号：EP3518108A1

公开(公告)日：2019-07-31

申请号：EP19154343.8

申请日：2019-01-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： NDU, Geoffrey ,  MILOJICIC, Dejan ,  CHALAMALASETTI, Sai Rahul

IPC: G06F9/50

Abstract: An example system includes at least one memristive dot product engine (DPE) having at least one resource, the DPE further having a physical interface and a controller, the controller being communicatively coupled to the physical interface, the physical interface to communicate with the controller to access the DPE, and at least one replicated interface, each replicated interface being associated with a virtual DPE, the replicated interface with communicatively coupled to the controller. The controller is to allocate timeslots to the virtual DPE through the associated replicated interface to allow the virtual DPE access to the at least one resource.