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公开(公告)号:WO2019212488A1
公开(公告)日:2019-11-07
申请号:PCT/US2018/030219
申请日:2018-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: CHALAMALASETTI, Sai Rahul , FARABOSCHI, Paolo , FOLTIN, Martin , GRAVES, Catherine , MILOJICIC, Dejan S. , STRACHAN, John Paul , SEREBRYAKOV, Sergey
IPC: G11C13/00
Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.
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公开(公告)号:WO2019212466A1
公开(公告)日:2019-11-07
申请号:PCT/US2018/030125
申请日:2018-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: STRACHAN, John Paul , MILOJICIC, Dejan S. , FOLTIN, Martin , CHALAMALASETTI, Sai Rahul , SHARMA, Amit S.
IPC: G06F15/78 , G06F15/163
Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.
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公开(公告)号:WO2017018978A1
公开(公告)日:2017-02-02
申请号:PCT/US2015/041899
申请日:2015-07-24
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: CHEN, Yuan , TALWAR, Vanish , MILOJICIC, Dejan S.
Abstract: In example implementations, a method is provided. The method includes receiving a job request at a scheduler of a plurality of schedulers based upon a quality of service (QoS) level associated with the job request and the scheduler. The job request is scheduled to a computing node based upon locally stored resource information of a selected number of computing nodes within a computing cluster. A shared memory is accessed via a memory fabric to obtain updated resource information of the selected number of computing nodes. The job request may then be re-scheduled to a different computing node based upon the updated resource information.
Abstract translation: 在示例实现中,提供了一种方法。 该方法包括:基于与作业请求和调度器相关联的服务质量(QoS)级别在多个调度器的调度器处接收作业请求。 基于计算集群内选定数量的计算节点的本地存储的资源信息,将作业请求调度到计算节点。 通过存储器结构访问共享存储器以获得所选数量的计算节点的更新的资源信息。 然后可以基于更新的资源信息将作业请求重新调度到不同的计算节点。
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公开(公告)号:WO2017131780A1
公开(公告)日:2017-08-03
申请号:PCT/US2016/015815
申请日:2016-01-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: EL HAJJ, Izzat , MERRITT, Alexander , ZELLWEGER, Gerd , MILOJICIC, Dejan S.
CPC classification number: G06F12/1009 , G06F2212/652
Abstract: Example implementations relate to identifying object modifications. In one example, identifying object modifications can employ a non-transitory processor readable medium including instructions to mark an entry in a pointer bounds table invalid, where the entry is associated with an object, attempt retrieval of pointer bounds associated with the entry in the pointer bounds table, and identify the object as modified when the pointer bounds are not retrieved.
Abstract translation: 示例实现涉及识别对象修改。 在一个示例中,识别对象修改可以采用包括指令的非暂时性处理器可读介质,以将指针边界表中的条目标记为无效,其中条目与对象相关联,尝试检索与指针中的条目相关联的指针边界 绑定表,并在未检索指针边界时将对象标识为已修改。 p>
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公开(公告)号:WO2017131747A1
公开(公告)日:2017-08-03
申请号:PCT/US2016/015661
申请日:2016-01-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: EL HAJJ, Izzat , MERRITT, Alexander , ZELLWEGER, Gerd , MILOJICIC, Dejan S.
CPC classification number: G06F12/109 , G06F9/4493 , G06F12/0238 , G06F2212/1016 , G06F2212/1032 , G06F2212/502 , G06F2212/657 , G06F2212/7202 , G06F2212/7207
Abstract: Example implementations relate to persistent virtual address spaces. In one example, persistent virtual address spaces can employ a non-transitory processor readable medium including instructions to receive a whole data structure of a virtual address space (VAS) associated with a process, where the whole data structure includes data and metadata of the VAS, and store the data and the metadata of the VAS in a non-volatile memory to form a persistent VAS (PVAS).
Abstract translation:
示例实现涉及持久虚拟地址空间。 在一个示例中,持久虚拟地址空间可以采用包括指令的非暂时性处理器可读介质,以接收与过程相关联的虚拟地址空间(VAS)的整个数据结构,其中整个数据结构包括VAS的数据和元数据 ,并将VAS的数据和元数据存储在非易失性存储器中以形成持久性VAS(PVAS)。 p>
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公开(公告)号:WO2016122585A1
公开(公告)日:2016-08-04
申请号:PCT/US2015/013748
申请日:2015-01-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: GERBER, Simon , MILOJICIC, Dejan S.
IPC: G11C7/10
CPC classification number: G11C7/10 , G06F3/061 , G06F3/0631 , G06F3/0673 , G06F11/3034 , G06F11/3452 , G06F12/0223 , G06F12/08
Abstract: A method of modifying characteristics of an existing memory segment in a virtual address space for a running software application. The existing memory segment includes an identification of a first backing memory region in physical memory for storing contents of the existing memory segment. The method includes tracking memory access statistics of the running software application, identifying new characteristics for the existing memory segment based on the tracked memory access statistics, and generating an updated memory segment that includes the identified new characteristics.
Abstract translation: 一种在运行的软件应用的虚拟地址空间中修改现有存储器段的特性的方法。 现有存储器段包括用于存储现有存储器段的内容的物理存储器中的第一后备存储器区域的标识。 该方法包括跟踪运行的软件应用的存储器访问统计信息,基于跟踪的存储器访问统计识别现有存储器段的新特性,以及生成包括所识别的新特性的更新的存储器段。
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公开(公告)号:WO2017131789A1
公开(公告)日:2017-08-03
申请号:PCT/US2016/015839
申请日:2016-01-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: EL HAJJ, Izzat , MERRITT, Alexander , ZELLWEGER, Gerd , MILOJICIC, Dejan S. , ACHERMANN, Reto
CPC classification number: G06F3/06 , G06F12/023 , G06F12/0292 , G06F2212/1012 , G06F2212/1044
Abstract: Examples disclosed herein include a memory management system, which includes a processor, and a write log to allow the processor to record write log entries, wherein each write log entry represents a write to main memory that has been performed. The system includes at least one table to facilitate versioning of in-memory objects stored in the main memory, and system software to track changes to the in-memory objects and create new versions of the in-memory objects using the write log and the at least one table.
Abstract translation: 这里公开的示例包括一种存储器管理系统,其包括处理器和允许处理器记录写入日志条目的写入日志,其中每个写入日志条目表示对主存储器的写入 执行。 该系统包括至少一个表格以便于对存储在主存储器中的存储器内对象进行版本控制,并且系统软件用于跟踪对存储器内对象的改变,并且使用写入日志创建新版本的存储器内对象, 至少有一个表。 p>
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公开(公告)号:WO2017131779A1
公开(公告)日:2017-08-03
申请号:PCT/US2016/015814
申请日:2016-01-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: EL HAJJ, Izzat , MERRITT, Alexander , ZELLWEGER, Gerd , MILOJICIC, Dejan S.
IPC: G06F12/08
CPC classification number: G06F12/1009 , G06F12/0246 , G06F12/145 , G06F2212/1052 , G06F2212/7207
Abstract: Example implementations relate to versioning virtual address spaces. In one example, versioning virtual address spaces can spaces can employ a non-transitory processor readable medium including instructions to store first data and first metadata of a VAS associated with a process in a non-volatile memory to form a first version of the VAS and store at least second data of the VAS associated with the process in the non-volatile memory to form a second version of the VAS.
Abstract translation:
示例实现涉及版本化虚拟地址空间。 在一个示例中,版本化虚拟地址空间可以空间可以采用包括指令的非暂时性处理器可读介质,以将与进程相关联的VAS的第一数据和第一元数据存储在非易失性存储器中以形成VAS的第一版本,并且 将与所述过程相关联的所述VAS的至少第二数据存储在所述非易失性存储器中以形成所述VAS的第二版本。 p>
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公开(公告)号:WO2017155523A1
公开(公告)日:2017-09-14
申请号:PCT/US2016/021446
申请日:2016-03-09
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: EL HAJJ, Izzat , MERRITT, Alexander , ZELLWEGER, Gerd , MILOJICIC, Dejan S.
CPC classification number: G06F9/4843 , G06F12/02 , G06F12/08 , G06F12/10 , G06F2212/657
Abstract: Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.
Abstract translation:
提供了客户端进程中的线程切换到服务器虚拟地址空间的技术。 在一个方面,过程可以附加到服务器虚拟地址空间。 可以从客户端进程内的客户端线程接收请求以从与客户端线程关联的虚拟地址空间切换到服务器虚拟地址空间。 客户端线程可以从客户端线程关联的虚拟地址空间切换到服务器虚拟地址空间。 p>
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公开(公告)号:WO2017044124A1
公开(公告)日:2017-03-16
申请号:PCT/US2015/049726
申请日:2015-09-11
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: EL HAJJ, Izzat , MERRITT, Alexander M. , ZELLWEGER, Gerd , MILOJICIC, Dejan S.
IPC: G06F12/10
CPC classification number: G06F9/5016
Abstract: Techniques for a process to switch virtual address spaces are provided, in one aspect, a request to switch from a first virtual address space to a second virtual address space may be received from a process. Process state information may be modified to reflect the change from the first virtual address space to the second virtual address space.
Abstract translation: 提供了用于切换虚拟地址空间的过程的技术,一方面,可以从进程接收到从第一虚拟地址空间切换到第二虚拟地址空间的请求。 可以修改处理状态信息以反映从第一虚拟地址空间到第二虚拟地址空间的改变。
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