公开(公告)号：JP2010118688A

公开(公告)日：2010-05-27

申请号：JP2010029399

申请日：2010-02-12

Applicant: Hrl Lab Llc ,  Raytheon Co ,  エイチアールエル ラボラトリーズ,エルエルシーHrl Laboratories, Llc ,  レイセオン カンパニーRaytheon Company

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L21/3205 ,  G06K19/073 ,  H01L21/822 ,  H01L23/52 ,  H01L23/58 ,  H01L27/04

CPC classification number: H01L27/0203 ,  G06K19/073 ,  G06K19/07363 ,  H01L23/573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a technique for and structures for camouflaging an integrated circuit structure against reverse engineering. SOLUTION: The integrated circuit structure is composed of a plurality of layers of material having a controlled outline. A layer of silicide metal is disposed in active areas of the substrate and has a gap over a channel connecting adjacent active areas. The channel has a channel block structure, which appears identical under reverse engineering whether it is made conductive or insulative. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为逆向工程提供集成电路结构伪装技术和结构。 解决方案：集成电路结构由具有受控轮廓的多层材料组成。 硅化金属层设置在衬底的有源区域中，并且在连接相邻有源区的沟道之间具有间隙。 通道具有通道块结构，无论是导电还是绝缘，在逆向工程中都是相同的。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：GB2422487B

公开(公告)日：2007-05-02

申请号：GB0607210

申请日：2003-09-23

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: G06K19/073 ,  H01L23/58

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

公开(公告)号：GB2412240A

公开(公告)日：2005-09-21

申请号：GB0512203

申请日：2005-06-15

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  BAUKUS JAMES P ,  HARBISON GAVIN J

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/76

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

公开(公告)号：WO2004049443A2

公开(公告)日：2004-06-10

申请号：PCT/US0337654

申请日：2003-11-20

Applicant: HRL LAB LLC ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L23/58 ,  H01L27/02

CPC classification number: H01L23/573 ,  H01L27/02 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique for and structres for camouflaging an integrated circuit structure. A layer ofconductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

Abstract translation: 用于伪装集成电路结构的技术和结构。 设置具有受控轮廓的导电材料层，以在实际上该装置不可操作时提供类似于可操作装置的导电材料的假象边缘。

公开(公告)号：GB2432971A

公开(公告)日：2007-06-06

申请号：GB0702704

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: The similarity of non-operable and operable transistors in an integrated circuit is increased by ensuring that the distance between the gate and source or drain electrodes is the same for both types of transistor. The use of non-operable transistors allow the circuit designer to disguise an AND gate so that it appears to be an OR gate to the reverse engineer. The disguised non-operable transistors cause the circuitry to operate in an unexpected manner to the reverse engineer.

公开(公告)号：GB2422956B

公开(公告)日：2007-05-23

申请号：GB0608053

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

公开(公告)号：AU2003293540A1

公开(公告)日：2004-07-09

申请号：AU2003293540

申请日：2003-12-10

Applicant: HRL LAB LLC

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P ,  HARBISON GAVIN J

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/76

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

公开(公告)号：WO2004055868A3

公开(公告)日：2004-10-07

申请号：PCT/US0339594

申请日：2003-12-10

Applicant: HRL LAB LLC ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P ,  HARBISON GAVIN J

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P ,  HARBISON GAVIN J

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/76

CPC classification number: H01L21/823892 ,  H01L27/02

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

Abstract translation: 用于伪装集成电路结构的技术和结构。 集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。 该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。

公开(公告)号：GB2413436B

公开(公告)日：2006-10-11

申请号：GB0511670

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

公开(公告)号：GB2422487A

公开(公告)日：2006-07-26

申请号：GB0607210

申请日：2003-09-23

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: G06K19/073 ,  H01L23/58

Abstract: An integrated circuit is protected from reverse engineering by providing conducting and non-conducting channels which appear identical. Active regions 22, 26 are connected by channel areas 23, 25 and pseudo channel-block structure 29 all of the same conductivity type. A layer of metal silicide is disposed over the active regions 22, 26 and channel areas 23, 25 but not the pseudo channel block structure 29. When reverse engineering techniques are applied edge artefacts 28 of the silicide covering a pseudo channel-blocked conducting channel appear identical to those of a non-conducting channel-blocked channel (figure 1B).