公开(公告)号：WO03001603A3

公开(公告)日：2003-03-27

申请号：PCT/EP0206919

申请日：2002-06-04

Applicant: IBM ,  IBM FRANCE

Inventor： AHLGREN DAVID C ,  FREEMAN GREGORY G ,  HUANG FENG YI ,  TICKNOR ADAM T

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L27/0623

Abstract: A process for forming a bipolar transistor with a raised extrinsic base (310) over the base (190), an emitter (350), and a buried collector (105) integrated with a CMOS transistor. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract translation: 用于在基极（190）上形成具有凸起的非本征基极（310）的双极晶体管的工艺，与CMOS晶体管集成的发射极（350）和掩埋集电极（105）。 提供具有CMOS和双极区域的中间半导体结构。 在双极区域内提供本征基层。 基底氧化物跨越形成，牺牲发射极堆叠硅层沉积在CMOS和双极区两者上。 施加光致抗蚀剂以保护双极区域，并且蚀刻该结构以从CMOS区域去除牺牲层，使得双极区域上的牺牲层的顶表面基本上与CMOS区域的顶表面齐平。 最后，沉积抛光停止层，其具有穿过适于随后的化学机械抛光（CMP）的CMOS和双极区域的基本平坦的顶表面，以形成凸起的外在基体。

公开(公告)号：JP2005167203A

公开(公告)日：2005-06-23

申请号：JP2004291416

申请日：2004-10-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AHLGREN DAVID C ,  GREGORY G FREEMAN ,  KHATER MARWAN H ,  VOLANT RICHARD P

IPC: H01L21/28 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor having self-aligned raised extrinsic base silicide and emitter contact border.
SOLUTION: The bipolar transistor exhibits the parasitic property which is more reduced than the parasitic property exhibited by a bipolar transistor which is not equipped with self-aligned silicide and a self-aligned emitter contact border. In a method of manufacturing the bipolar transistor structure, a block emitter polysilicon region is replaced with a conventional T-shaped emitter polysilicon.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有自对准凸起的外在基极硅化物和发射极接触边界的双极晶体管。 解决方案：双极晶体管表现出比由不配置自对准硅化物和自对准发射极接触边界的双极晶体管表现出的寄生特性降低的寄生特性。 在制造双极晶体管结构的方法中，块状发射极多晶硅区域被传统的T形发射极多晶硅替代。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004193575A

公开(公告)日：2004-07-08

申请号：JP2003380487

申请日：2003-11-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NATZLE WESLEY C ,  AHLGREN DAVID C ,  BARBEE STEVEN G ,  CANTELL MARC W ,  JAGANNATHAN BASANTH ,  LANZEROTTI LOUIS D ,  SUBBANNA SESHARDI ,  RYAN W WOOTHRICH

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/732

CPC classification number: H01L29/66242 ,  H01L21/31116 ,  H01L21/8249

Abstract: PROBLEM TO BE SOLVED: To provide an oxide etching process that can be used for manufacturing the emitter and base in a bipolar SiGe device. SOLUTION: The low-temperature process used gives electric insulation between the emitters and bases by COR (chemical oxide removal) etching protecting the insulating TEOS (tetraethylorthosilicate) glass 22. The insulating TEOS glass 22 brings about the capacitance reduction, and promotes to achieve high-speed. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004319983A

公开(公告)日：2004-11-11

申请号：JP2004085745

申请日：2004-03-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SUBBANNA SESHADRI ,  JAGANNATHAN BASANTH ,  GREGORY G FREEMAN ,  AHLGREN DAVID C ,  ANGELL DAVID ,  SCHONENBERG KATHRYN T ,  STEIN KENNETH J ,  JAMIN FEN F

IPC: H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78

CPC classification number: H01L21/8249 ,  H01L27/0623

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a BiCMOS integrated circuit having a raised external base.
SOLUTION: This method comprises a step for forming a polycrystal silicon layer on the surface of a gate dielectric substance 18 provided on a substrate having a device section 14 in which a bipolar transistor is formed and a device section 16 in which a CMOS transistor is formed. Then, the polycrystal silicon layer is patterned, and a sacrifice polycrystal silicon layer is formed above the device section in which the bipolar transistor is formed and the section around it. Meanwhile, a gate conductor is provided in the device section in which the CMOS transistor is formed at the same time. Then, a spacer 30 is provided around each of the gate conductor. Then a part of the sacrifice polycrystal silicon layer on the bipolar device section is selectively removed to provide an opening in the device section in which the bipolar transistor is formed. Then the bipolar transistor having a raised external base 58 is formed at the opening.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成具有凸起的外部基底的BiCMOS集成电路的方法。 解决方案：该方法包括在设置在其上形成有双极晶体管的器件部分14的衬底上的栅极电介质18的表面上形成多晶硅层的步骤，以及器件部分16，其中CMOS 形成晶体管。 然后，对多晶硅层进行构图，在形成双极型晶体管的器件部分上方形成牺牲多晶硅层，并在其周围形成截面。 同时，在同时形成CMOS晶体管的器件部分中提供栅极导体。 然后，围绕每个栅极导体设置间隔件30。 然后，选择性地去除双极器件部分上牺牲多晶硅层的一部分，以在其中形成双极晶体管的器件部分中提供开口。 然后在开口处形成具有升高的外部基座58的双极晶体管。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：CA1238118A

公开(公告)日：1988-06-14

申请号：CA501735

申请日：1986-02-12

Applicant: IBM

Inventor： AHLGREN DAVID C ,  MA WILLIAM H ,  REVITZ MARTIN

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/425

Abstract: A method, useful in fabricating semiconductor integrated circuits, for passivating an undercut formed by etch-back of a silicon dioxide layer under a diverse insulator film is disclosed. The method includes the step of coating the device with a thin, conformal film to a thickness sufficient only to line, without refilling, the lateral walls of the undercut region.

公开(公告)号：AT333708T

公开(公告)日：2006-08-15

申请号：AT02754739

申请日：2002-06-04

Applicant: IBM

Inventor： AHLGREN DAVID C ,  FREEMAN GREGORY G ,  HUANG FENG YI ,  TICKNOR ADAM T

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

公开(公告)号：AU2002321102A1

公开(公告)日：2003-01-08

申请号：AU2002321102

申请日：2002-06-04

Applicant: IBM

Inventor： FREEMAN GREGORY G ,  HUANG FENG YI ,  TICKNOR ADAM T ,  AHLGREN DAVID C

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.