公开(公告)号：WO03001603A3

公开(公告)日：2003-03-27

申请号：PCT/EP0206919

申请日：2002-06-04

Applicant: IBM ,  IBM FRANCE

Inventor： AHLGREN DAVID C ,  FREEMAN GREGORY G ,  HUANG FENG YI ,  TICKNOR ADAM T

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L27/0623

Abstract: A process for forming a bipolar transistor with a raised extrinsic base (310) over the base (190), an emitter (350), and a buried collector (105) integrated with a CMOS transistor. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract translation: 用于在基极（190）上形成具有凸起的非本征基极（310）的双极晶体管的工艺，与CMOS晶体管集成的发射极（350）和掩埋集电极（105）。 提供具有CMOS和双极区域的中间半导体结构。 在双极区域内提供本征基层。 基底氧化物跨越形成，牺牲发射极堆叠硅层沉积在CMOS和双极区两者上。 施加光致抗蚀剂以保护双极区域，并且蚀刻该结构以从CMOS区域去除牺牲层，使得双极区域上的牺牲层的顶表面基本上与CMOS区域的顶表面齐平。 最后，沉积抛光停止层，其具有穿过适于随后的化学机械抛光（CMP）的CMOS和双极区域的基本平坦的顶表面，以形成凸起的外在基体。

公开(公告)号：EP2409332A4

公开(公告)日：2012-01-25

申请号：EP10753837

申请日：2010-02-11

Applicant: IBM

Inventor： CHOU ANTHONY I ,  FREEMAN GREGORY G ,  MCSTAY KEVIN ,  NARASIMHA SHREESH

IPC: H01L29/739 ,  H01L21/285 ,  H01L21/329 ,  H01L21/33 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L21/28518 ,  H01L21/76829 ,  H01L29/66356 ,  H01L29/7391

公开(公告)号：EP1745515A4

公开(公告)日：2009-04-01

申请号：EP04822011

申请日：2004-04-22

Applicant: IBM

Inventor： FREEMAN GREGORY G ,  RIEH JAE-SUNG ,  SHERIDAN DAVID C ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D ,  VOLDMAN STEVEN H

IPC: H01L29/00 ,  H01L21/331 ,  H01L21/332 ,  H01L29/08 ,  H01L29/737 ,  H01L29/74 ,  H01L29/861 ,  H01L29/872 ,  H01L29/93

CPC classification number: H01L29/66363 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/66242 ,  H01L29/7378 ,  H01L29/74 ,  H01L29/861 ,  H01L29/872 ,  H01L29/93

Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.

公开(公告)号：JP2002324806A

公开(公告)日：2002-11-08

申请号：JP2002075491

申请日：2002-03-19

Applicant: IBM

Inventor： FREEMAN GREGORY G ,  JAGANNATHAN BASANTH ,  JENG SHWU-JEN ,  JOHNSON JEFFREY B

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/36 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide an element structure and a method for manufacturing the same for suppressing an increase of an unnecessary capacitance in the element as small as possible and for improving a transistor characteristic. SOLUTION: In an integrated bi-polar circuit element, a stepped collector dopant profile reduces a transit time and a parasitic capacitance between an emitter and a collector due to a minimum increase of the parasitic capacitance. A shallow implantation reduces a width of a space charge region between a base and the collector, reduces a resistance, and individually optimizes a breakdown characteristic between the collector and the base. A deep implantation, then, links a buried collector to a sub-collector and provides a low resistance path to the sub-collector. The stepped collector dopant profile only gives the lowest effect against a capacitance the collector and the base outside an intrinsic region of the element. The reason is that the higher concentration dopant is compensated by an exogenous dopant outside the intrinsic region or is buried therein.

公开(公告)号：AT333708T

公开(公告)日：2006-08-15

申请号：AT02754739

申请日：2002-06-04

Applicant: IBM

Inventor： AHLGREN DAVID C ,  FREEMAN GREGORY G ,  HUANG FENG YI ,  TICKNOR ADAM T

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

公开(公告)号：AU2002321102A1

公开(公告)日：2003-01-08

申请号：AU2002321102

申请日：2002-06-04

Applicant: IBM

Inventor： FREEMAN GREGORY G ,  HUANG FENG YI ,  TICKNOR ADAM T ,  AHLGREN DAVID C

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/737

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.