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    Semiconductor device with beta tantalum-gold composite conductor metallurgy
    3.
    发明授权
    Semiconductor device with beta tantalum-gold composite conductor metallurgy 失效
    具有铂金属复合导体金属的半导体器件

    公开(公告)号：US3641402A

    公开(公告)日：1972-02-08

    申请号：US3641402D

    申请日：1969-12-30

    Applicant: IBM

    Inventor： REVITZ MARTIN ,  TURENE FRANCIS E

    IPC: H01L23/482 ,  H01L23/532 ,  H01L1/14

    CPC classification number: H01L23/53242 ,  H01L23/4822 ,  H01L24/01 ,  H01L2924/01322 ,  H01L2924/00

    Abstract: A deposited film of gold is adhered to a layer of silicon dioxide by a deposited film of Beta tantalum. After the gold is deposited on the Beta tantalum, a second film of Beta tantalum is deposited on the gold. This forms a composite sandwich adhering the gold to the silicon dioxide without decreasing the conductivity of the gold and allowing another layer of silicon dioxide to be adhered to the second film of Beta tantalum.

    Abstract translation: 通过沉积的β钽膜将沉积的金膜附着到二氧化硅层上。 在金沉积在β钽上之后，第二层β钽沉积在金上。 这形成了将金粘附到二氧化硅上而不降低金的导电性并允许另一层二氧化硅粘附到第二薄膜的钽的复合夹层。

    Stabilisation of gate dielectric layer - in metal oxide semiconductor devices to reduce fixed oxide charge in layer
    4.
    发明专利
    Stabilisation of gate dielectric layer - in metal oxide semiconductor devices to reduce fixed oxide charge in layer 未知

    公开(公告)号：FR2290757A1

    公开(公告)日：1976-06-04

    申请号：FR7529327

    申请日：1975-09-19

    Applicant: IBM

    Inventor： GOULA ROBERT A ,  RAIDER STANLEY I ,  REVITZ MARTIN

    IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/18 ,  H01L29/78

    Abstract: Method of mfr. and stabilisation of a gate dielectric layer in MOS devices in order to reduce the fixed oxide charge in the gate duelectric layer without degrading the characteristic of the layer comprises forming a layer of >=1 SiO2, layer 500A thick on >=1 region of the gate by thermal oxidation of the monocrystalline silicon substrate and reheating the substrate in an atmosphere of He, Ne, Ar, Kr, or Xe, at 900 degrees C for >=10 mins. The gate dielectric layer is 100-300 A thick. The substrate is heated at 900-1100 degrees C for 9 mins to 100 hrs. pref. at 950-1050 degrees C for 15 mins to 24 hrs. in argon. The heat treatment in inert gas reduces the state of charge of the surface while N2 does not.

    METAL-INSULATOR-SEMICONDUCTOR DEVICE MANUFACTURE
    5.
    发明专利
    METAL-INSULATOR-SEMICONDUCTOR DEVICE MANUFACTURE 未知

    公开(公告)号：CA1120605A

    公开(公告)日：1982-03-23

    申请号：CA337620

    申请日：1979-10-15

    Applicant: IBM

    Inventor： GARDINER JAMES R ,  PLISKIN WILLIAM A ,  REVITZ MARTIN ,  SHEPARD JOSEPH F

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L21/20

    Abstract: METAL-INSULATOR-SEMICONDUCTOR DEVICE MANUFACTURE A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved. FI 9-77-065

    PROCESS FOR THE MANUFACTURE OF FIELD-EFFECT TRANSISTORS
    6.
    发明专利
    PROCESS FOR THE MANUFACTURE OF FIELD-EFFECT TRANSISTORS 未知

    公开(公告)号：DE2967090D1

    公开(公告)日：1984-08-09

    申请号：DE2967090

    申请日：1979-11-19

    Applicant: IBM

    Inventor： GARDINER JAMES ROBERT ,  PLISKIN WILLIAM AARON ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L21/00

    Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

    8.
    发明专利
    未知

    公开(公告)号：IT1165429B

    公开(公告)日：1987-04-22

    申请号：IT2812579

    申请日：1979-12-18

    Applicant: IBM

    Inventor： GARDINER JAMES ROBERT ,  PLISKIN WILLIAM AARON ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L

    Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

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