公开(公告)号：DE60233241D1

公开(公告)日：2009-09-17

申请号：DE60233241

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H ,  RABIDOUX PAUL A

IPC: H01L29/76 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

Abstract: A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

公开(公告)号：CA1238118A

公开(公告)日：1988-06-14

申请号：CA501735

申请日：1986-02-12

Applicant: IBM

Inventor： AHLGREN DAVID C ,  MA WILLIAM H ,  REVITZ MARTIN

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/425

Abstract: A method, useful in fabricating semiconductor integrated circuits, for passivating an undercut formed by etch-back of a silicon dioxide layer under a diverse insulator film is disclosed. The method includes the step of coating the device with a thin, conformal film to a thickness sufficient only to line, without refilling, the lateral walls of the undercut region.