公开(公告)号：JP2002312080A

公开(公告)日：2002-10-25

申请号：JP2002055192

申请日：2002-03-01

Applicant: IBM

Inventor： YAMAZAKI SATORU ,  ISHIMOTO KENJI ,  KIGOSHI TSUTOMU

IPC: G06F1/32

Abstract: PROBLEM TO BE SOLVED: To provide an improved power management device and method for a personal computer. SOLUTION: In a computer system shifting to a power saving mode when there is no user input from a keyboard and the like for a fixed period of time, a circuit detecting writing to a video memory and a power management controlling program for controlling power cooperating with the circuit are used. When writing to the video memory is detected, shifting to the power saving mode is prohibited even if there is no input from the keyboard and the like for the fixed period of time.

公开(公告)号：JPH11312968A

公开(公告)日：1999-11-09

申请号：JP11714998

申请日：1998-04-27

Applicant: IBM

Inventor： SUZUKI KEIJI ,  YAMAZAKI SATORU

IPC: H02H9/04 ,  G06F1/26 ,  H03K17/00 ,  H03K17/06 ,  H03K17/687

Abstract: PROBLEM TO BE SOLVED: To provide a simple switch circuit equipped with a remaining voltage elimination function of high reliability. SOLUTION: This switch circuit has a first switch 101 equipped with a first terminal connected to a first power source terminal, a second terminal connected to a power source output terminal and a control terminal connected to a first control terminal, a second switch 103 equipped with the first terminal connected to the control terminal of the first switch 101, the second terminal connected to a second power source terminal and the control terminal connected to a second control signal terminal, and a reverse flow prevention element 107 connected between the power source output terminal and the first terminal of the second switch 103. Even if the second switch 103 breaks down, it can be easily found, and a futile current does not flow from the power source output terminal into the second power source terminal.

公开(公告)号：JP2004145733A

公开(公告)日：2004-05-20

申请号：JP2002311403

申请日：2002-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YAMAZAKI SATORU ,  KUBOTA TORU ,  FUJITA NORIO

IPC: G06F12/00 ,  G06F12/06 ,  G11C16/20

CPC classification number: G11C16/20 ,  G11C2029/4402

Abstract: PROBLEM TO BE SOLVED: To enable the identification of a memory module without requiring the addition of a part to a computer body side or the providing of a ROM recording a specification or the like on the memory module side. SOLUTION: The memory module having a memory array 1 for storing data comprises an ID information output circuit 2 for outputting ID information for identifying the memory module, and an output switching means 3 for selectively switching and outputting the output from the memory array and the output from the ID information output circuit. The output from the ID information output circuit 2 is selected instead of the output from the memory array 1 until writing is performed first to the memory module after the start of power supply to the memory module. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003044177A

公开(公告)日：2003-02-14

申请号：JP2001212766

申请日：2001-07-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： KATO ATSUYUKI ,  YAMAZAKI SATORU ,  KOSUGI CHIEI ,  YOSHIYAMA NORITOSHI ,  YOMO TAKATSUGU

IPC: G06F1/26

Abstract: PROBLEM TO BE SOLVED: To provide a computer system, a power supply managing method, etc., capable of performing power supply rich in variation. SOLUTION: This computer system performs power supply control in a gate array 42 based on an indication of an OS and a BIOS on an on mode with respect to a bay device 33 connected to a bay 32, and performs power supply control by an embedded controller 41 in a sleep mode and an off mode. By using an OR gate 71, setting is performed so that output signals (BAY- ON- EC and BAY- ON- GA) from the embedded controller 41 and the gate array 42 do not interfere with each other.

Abstract translation: 要解决的问题：提供能够进行变化丰富的电源的计算机系统，电源管理方法等。 解决方案：该计算机系统基于相对于连接到托架32的托架设备33的on模式的OS和BIOS的指示，在门阵列42中执行电源控制，并且由嵌入式控制器执行电源控制 41处于睡眠模式和关闭模式。 通过使用或门71，进行设定，使得来自嵌入式控制器41和门阵列42的输出信号（BAY-ON-EC和BAY-ON-GA）不彼此干扰。

公开(公告)号：JPH09160736A

公开(公告)日：1997-06-20

申请号：JP30866895

申请日：1995-11-28

Applicant: IBM

Inventor： YAMAZAKI SATORU ,  FUJITA NORIO

IPC: G06F3/14 ,  G06T3/00 ,  G09G5/00 ,  G09G5/36 ,  G09G5/377 ,  G09G5/39 ,  G09G5/395

Abstract: PROBLEM TO BE SOLVED: To provide the overlay function by hardware which solves the problem points of a conventional overlay system by addition to a general graphic controller. SOLUTION: This processing circuit has an address search circuit, an internal video memory 506, and an overlay data processing circuit 503. The address search circuit always monitors an object address at the time of the read operation of the graphic controller 502 and the internal video memory 506 stores image data to be overlaid. When a read address specified by the graphic controller 502 enters an address area to be overlaid, the image data from the internal video memory 506 are transferred to the graphic controller 502 instead of image data from an ordinary video memory.

公开(公告)号：JPH09128105A

公开(公告)日：1997-05-16

申请号：JP27248395

申请日：1995-10-20

Applicant: IBM

Inventor： YAMAZAKI SATORU ,  ISHIMOTO KENJI ,  KIGOSHI TSUTOMU

IPC: G06F1/32 ,  G06F15/02

Abstract: PROBLEM TO BE SOLVED: To inhibit transition from an ordinary power-on state to a power- saving mode that a user does not desire by the power-saving function of a personal computer and to make the power-saving function easier to use. SOLUTION: A computer system which enters power-saving mode unless there is user input from a keyboard, etc., for a certain time uses a circuit which detects writing to a video memory and a power source management control program which performs power-source management in cooperation with the said circuit. When the video memory is written, the shift to the power-saving mode is inhibited even if there is no input from the keyboard, etc., for the certain time.

公开(公告)号：JPH06250937A

公开(公告)日：1994-09-09

申请号：JP2110593

申请日：1993-02-09

Applicant: IBM

Inventor： FUJITA NORIO ,  FUJITA NOBUHITO ,  YAMAZAKI SATORU ,  AIDA MITSUHIRO

IPC: G06F11/10 ,  G06F12/16

Abstract: PURPOSE: To suppress the increase of the number of times of memory access at the time of adding an ECC code to each data with specific length and operating an ECC processing, and to prevent the executing speed of a program from being sharply deteriorated even at the time of executing the ECC processing. CONSTITUTION: At the time of adding an ECC code to each data with specific bit length and writing the data in a memory element 20, when the length of writing data from a CPU 10 is less than the specific bit length, data previously read from the memory element 20 are held in a mean 42 different from the memory element 20, and data with the specific bit length are generated based on the held data and the writing data from the CPU 10. Thus, the ECC processing can be attained even when the reading from the memory is not necessarily operated before the writing in the memory.

公开(公告)号：JPH05127994A

公开(公告)日：1993-05-25

申请号：JP29040791

申请日：1991-10-11

Applicant: IBM

Inventor： FUKUSHIMA TOSHIAKI ,  AIDA MITSUHIRO ,  YAMAZAKI SATORU

IPC: G06F12/08 ,  G06F12/16

Abstract: PURPOSE: To quickly attain the test of a system memory by fetching a code part in a test program in a cache memory, and by not fetching a data part in the cache memory. CONSTITUTION: A cache memory 40 and a stage signal generating means 42 are incorporated in a microprocessor (CPU) 10. The cache memory 40 is enabled or disabled by a cache control signal inputted to the CPU 10. The sate signal generating means 42 generates a data/code signal (+D/-C signal) indicating whether the CPU 10 performs access to the code part of a program stored in a system memory 30 or performs access to the data part. When the +D/-D signal is a high level, the CPU 10 performs access to the data part, and when the +D/-D signal is a low level, the CPU 10 performs access to the code part.