公开(公告)号：JP2005018329A

公开(公告)日：2005-01-20

申请号：JP2003180841

申请日：2003-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOMURA TAICHIRO ,  FUKUSHIMA TOSHIAKI ,  MATSUI YOICHI

IPC: G06F12/06 ,  G06F1/04 ,  G06F1/20 ,  G06F12/00 ,  G06F13/16

CPC classification number: G11C29/028 ,  G06F13/1694 ,  G11C7/04 ,  G11C29/50012 ,  G11C2029/4402 ,  G11C2029/5002

Abstract: PROBLEM TO BE SOLVED: To appropriately control an access to a memory module. SOLUTION: A setting device which sets up a memory control unit for accessing a memory module which mounts a memory device is equipped with a memory attribute information acquiring section which acquires memory attribute information which indicates the attributes of the memory module from an attribute memory prepared in the memory module; a transfer rate setting section which decides a data transfer rate setting value which is a ratio of an upper limit of data transfer rate for accessing a memory module by a memory control unit against a maximum data transfer rate accessing the memory module by the memory control unit in accordance with the memory attribute information, and sets it in the memory control unit. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：适当地控制对存储器模块的访问。 解决方案：设置用于访问安装存储器件的存储器模块的存储器控​​制单元的设置装置配备有存储器属性信息获取部件，其从属性获取指示存储器模块的属性的存储器属性信息 内存在内存模块中准备; 决定数据传送速度设定值，该数据传送速度设定值是由存储器控制单元访问存储器模块的数据传送速率的上限与由存储器控制单元访问存储器模块的最大数据传送速率的比率 根据存储器属性信息，并将其设置在存储器控制单元中。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH05127994A

公开(公告)日：1993-05-25

申请号：JP29040791

申请日：1991-10-11

Applicant: IBM

Inventor： FUKUSHIMA TOSHIAKI ,  AIDA MITSUHIRO ,  YAMAZAKI SATORU

IPC: G06F12/08 ,  G06F12/16

Abstract: PURPOSE: To quickly attain the test of a system memory by fetching a code part in a test program in a cache memory, and by not fetching a data part in the cache memory. CONSTITUTION: A cache memory 40 and a stage signal generating means 42 are incorporated in a microprocessor (CPU) 10. The cache memory 40 is enabled or disabled by a cache control signal inputted to the CPU 10. The sate signal generating means 42 generates a data/code signal (+D/-C signal) indicating whether the CPU 10 performs access to the code part of a program stored in a system memory 30 or performs access to the data part. When the +D/-D signal is a high level, the CPU 10 performs access to the data part, and when the +D/-D signal is a low level, the CPU 10 performs access to the code part.

公开(公告)号：JP2005004600A

公开(公告)日：2005-01-06

申请号：JP2003169127

申请日：2003-06-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FUKUSHIMA TOSHIAKI ,  NOMURA TAICHIRO ,  TANAKA JUN ,  OSHITA SHIGERU

IPC: G05D23/19 ,  G06F1/20

CPC classification number: G06F1/20 ,  G05D23/1931 ,  G06F1/206

Abstract: PROBLEM TO BE SOLVED: To provide an information processor capable of adjusting the set temperature for executing temperature control processing, depending on the characteristics of the information processor. SOLUTION: The information processor comprises: a central processing unit; a temperature control information storage section storing the temperature control processing performed for lowering the temperature of the central processing unit while corresponding to the set temperature; a temperature measurement section for measuring the temperature at a measurement location in the central processing unit; a temperature detection section for detecting the fact that the temperature at a detection location in the central processing unit reaches the detection temperature; an offset calculation section calculating offset, a difference between the temperature measured by the temperature measurement section and the detection temperature at the time of detecting the temperature by the temperature detection section; a set temperature correction section calculating the correction value of the setting temperature stored on the temperature control information storage section based on the offset; and a temperature control execution section executing the temperature control processing stored on the temperature control information storage section while corresponding to the set temperature when the temperature measured by the temperature measurement section reaches the correction value of the set temperature. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够根据信息处理器的特性来调节用于执行温度控制处理的设定温度的信息处理器。 解决方案：信息处理器包括：中央处理单元; 温度控制信息存储部，存储对应于设定温度而进行的用于降低中央处理单元的温度的温度控制处理; 用于测量中央处理单元中的测量位置处的温度的温度测量部分; 温度检测部，用于检测中央处理单元中的检测位置处的温度达到检测温度的事实; 偏移计算部，计算偏差，由所述温度测量部测量的温度与由所述温度检测部检测温度时的检测温度之间的差; 设定温度校正部，基于所述偏移来计算存储在所述温度控制信息存储部的所述设定温度的修正值; 以及温度控制执行部，其在由所述温度测量部测量的温度达到设定温度的修正值的同时对应于设定温度执行存储在所述温度控制信息存储部上的所述温度控制处理。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH08305629A

公开(公告)日：1996-11-22

申请号：JP10105995

申请日：1995-04-25

Applicant: IBM

Inventor： FUKUSHIMA TOSHIAKI ,  OISHI SHINJI ,  NOMURA MASAHIKO

IPC: G06F12/06 ,  G06F13/16 ,  G11C5/00 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401

Abstract: PURPOSE: To dynamically compensate the signal waveform or timing of each output signal line (RAS, CAS, WE, MA) of a memory controller even when many kinds of extended memories (DIMM card) whose storage capacities or memory chip arrays are different are mounted. CONSTITUTION: This is a memory access controller used for a computer system on which an extended memory 17 can be mounted in addition to a standard memory 13, which controls access to the memories 13 and 17 by more than one signal lines. This memory access controller is provided with an identifying means which reads the identification data of the mounted extended memory 17, discriminating means which discriminates the optimal output current value of each signal line based on the identification data, and means which adjusts the output currents of each signal line based on the discriminated result.