公开(公告)号：SG106644A1

公开(公告)日：2004-10-29

申请号：SG200106659

申请日：2001-10-30

Applicant: IBM

Inventor： JOHN M COHN ,  ALVAR A DEAN ,  DAVID J HATHAWAY ,  DAVID E LACKEY ,  THOMAS E LEPSIC ,  SUSAN K LICHTENSTEIGER ,  SCOTT A TETREAULT ,  SEBASTIAN THEODORE VENTRONE

IPC: G06F17/50 ,  H01L21/82

Abstract: Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into "bins", which are areas of the design. In this way, a semiconductor chip design may be "sliced" into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.

公开(公告)号：SG90108A1

公开(公告)日：2002-07-23

申请号：SG200001383

申请日：2000-03-10

Applicant: IBM

Inventor： ALVAR A DEAN ,  KENNETH J GOODNOW ,  PATRICK E PERRY ,  SEBASTIAN THEODORE VENTRONE

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/38 ,  G06F15/78 ,  G06F13/10 ,  G06F17/00 ,  G05F1/10

Abstract: A processor with multiple equivalent functional units for power reduction, which includes a mechanism for controlling the selection of functional units. Specifically, the processor comprises a first circuit performing a predetermined function at a first speed, a second circuit for performing the same predetermined function at a second speed, and a control system for selecting either the first or second circuit to perform the function. The control system further includes a mechanism for controlling the rate of execution of the processor instructions in the pipeline in order to compensate for the speed at which the first or second circuit was performing the predetermined function.