公开(公告)号：GB2579487A

公开(公告)日：2020-06-24

申请号：GB202001682

申请日：2018-07-16

Applicant: IBM ,  GLOBALFOUNDRIES INC ,  SAMSUNG ELECTRONICS CO LTD

Inventor： SU CHEN FAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ANDREW GREENE ,  RUILONG XIE ,  MARK VICTOR RAYMOND ,  SEAN LIAN

IPC: H01L21/8238

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided, in one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers In a dielectric; forming gate trenches by selectively rernoving the dielectric from: regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：GB2579487B

公开(公告)日：2021-12-15

申请号：GB202001682

申请日：2018-07-16

Applicant: IBM ,  GLOBALFOUNDRIES INC ,  SAMSUNG ELECTRONICS CO LTD

Inventor： SU CHEN FAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ANDREW GREENE ,  RUILONG XIE ,  MARK VICTOR RAYMOND ,  SEAN LIAN

IPC: H01L21/768 ,  H01L21/8238

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：GB2579463B

公开(公告)日：2022-03-02

申请号：GB202001032

申请日：2018-06-25

Applicant: IBM

Inventor： GAURI KARVE ,  PIETRO MONTANINI ,  ERIC MILLER ,  SIVANANDA KANAKASABAPATHY ,  ANDREW GREENE

IPC: H01L21/8238 ,  H01L29/78

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：GB2579463A

公开(公告)日：2020-06-24

申请号：GB202001032

申请日：2018-06-25

Applicant: IBM

Inventor： GAURI KARVE ,  PIETRO MONTANINI ,  ERIC MILLER ,  SIVANANDA KANAKASABAPATHY ,  ANDREW GREENE

IPC: H01L21/8238 ,  H01L29/78

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).